From: Stefan Rebernig Date: Fri, 17 Dec 2010 21:47:04 +0000 (+0100) Subject: nochmal... X-Git-Tag: bootrom_v1~44^2~23 X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=calu.git;a=commitdiff_plain;h=8dd0b1556d1726952e776954a6b2ca9ae357491c nochmal... --- diff --git a/cpu/src/extension_7seg.vhd b/cpu/src/extension_7seg.vhd new file mode 100755 index 0000000..528ceda --- /dev/null +++ b/cpu/src/extension_7seg.vhd @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.common_pkg.all; +use work.extension_pkg.all; +use work.extension_7seg_pkg.all; + +entity extension_7seg is + + generic( + RESET_VALUE : std_logic + ); + port( + --System inputs + sys_clk : in std_logic; + sys_res_n : in std_logic; + -- general extension interface + ext_reg : in extmod_rec; +-- data_out : out gp_register_t; + --Control input +-- val : in std_logic_vector(4 downto 0); +-- pos : in std_logic_vector(1 downto 0); +-- act : std_logic; + --Output + o_digit0 : out std_logic_vector(0 to 6); + o_digit1 : out std_logic_vector(0 to 6); + o_digit2 : out std_logic_vector(0 to 6); + o_digit3 : out std_logic_vector(0 to 6) + ); + +end extension_7seg; diff --git a/cpu/src/extension_7seg_b.vhd b/cpu/src/extension_7seg_b.vhd new file mode 100755 index 0000000..0e58cca --- /dev/null +++ b/cpu/src/extension_7seg_b.vhd @@ -0,0 +1,86 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +--use work.math_pkg.all; +use work.common_pkg.all; +use work.core_pkg.all; + +use work.mem_pkg.all; +use work.extension_pkg.all; +use work.extension_7seg_pkg.all; + +architecture behav of extension_7seg is + +signal s_state, s_state_nxt : sseg_state_rec; +signal ext_reg_r : extmod_rec; + +begin + +seg_syn: process(sys_clk, sys_res_n) + +begin + + if (sys_res_n = RESET_VALUE) then + + s_state.digit0 <= (others => '0');--set(0,7); + s_state.digit1 <= (others => '0');--set(0,7); + s_state.digit2 <= (others => '0');--set(0,7); + s_state.digit3 <= (others => '0');--set(0,7); + + ext_reg_r.sel <='0'; + ext_reg_r.wr_en <= '0'; + ext_reg_r.byte_en <= (others => '0'); + ext_reg_r.data <= (others => '0'); + ext_reg_r.addr <= (others => '0'); + + elsif rising_edge(sys_clk) then + + s_state <= s_state_nxt; + ext_reg_r <= ext_reg; + + end if; + +end process; + +seg_asyn: process(s_state, ext_reg_r) + +variable tmp_data : byte_t; + +begin + s_state_nxt <= s_state; + tmp_data := (others =>'0'); + + if ext_reg_r.sel = '1' and ext_reg_r.wr_en = '1' then + + tmp_data(byte_t'range) :=ext_reg_r.data(byte_t'range); + + s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0)); + s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4)); + s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8)); + s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12)); + + case ext_reg_r.byte_en(1 downto 0) is + when "01" => s_state_nxt.digit3 <= digit_decode("11111"); + when "00" => null; + when "10" => null; + when "11" => null; + when others => null; + end case; + + + end if; + +end process; --ps2_next + +seg_out: process(s_state) +begin + + o_digit0 <= not(s_state.digit0); + o_digit1 <= not(s_state.digit1); + o_digit2 <= not(s_state.digit2); + o_digit3 <= not(s_state.digit3); + +end process; + +end behav; diff --git a/cpu/src/extension_7seg_pkg.vhd b/cpu/src/extension_7seg_pkg.vhd new file mode 100755 index 0000000..30b3414 --- /dev/null +++ b/cpu/src/extension_7seg_pkg.vhd @@ -0,0 +1,103 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.common_pkg.all; +use work.extension_pkg.all; + +package extension_7seg_pkg is + + constant SEGMENT_G : std_logic_vector(0 to 6) := "0000001"; + constant SEGMENT_F : std_logic_vector(0 to 6) := "0000010"; + constant SEGMENT_E : std_logic_vector(0 to 6) := "0000100"; + constant SEGMENT_D : std_logic_vector(0 to 6) := "0001000"; + constant SEGMENT_C : std_logic_vector(0 to 6) := "0010000"; + constant SEGMENT_B : std_logic_vector(0 to 6) := "0100000"; + constant SEGMENT_A : std_logic_vector(0 to 6) := "1000000"; + + constant DIGIT_0 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_C or SEGMENT_D or SEGMENT_E or SEGMENT_F; + constant DIGIT_1 : std_logic_vector(0 to 6) := SEGMENT_B or SEGMENT_C; + constant DIGIT_2 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_G or SEGMENT_E or SEGMENT_D; + constant DIGIT_3 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_C or SEGMENT_D or SEGMENT_G; + constant DIGIT_4 : std_logic_vector(0 to 6) := SEGMENT_B or SEGMENT_C or SEGMENT_G or SEGMENT_F; + constant DIGIT_5 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_G or SEGMENT_C or SEGMENT_D; + constant DIGIT_6 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_E or SEGMENT_D or SEGMENT_C or SEGMENT_G; + constant DIGIT_7 : std_logic_vector(0 to 6) := SEGMENT_A or DIGIT_1; + constant DIGIT_8 : std_logic_vector(0 to 6) := SEGMENT_G or DIGIT_0; + constant DIGIT_9 : std_logic_vector(0 to 6) := SEGMENT_B or DIGIT_5; + constant DIGIT_A : std_logic_vector(0 to 6) := DIGIT_1 or SEGMENT_A or SEGMENT_G or SEGMENT_E or SEGMENT_F; + constant DIGIT_B : std_logic_vector(0 to 6) := SEGMENT_F or SEGMENT_E or SEGMENT_D or SEGMENT_C or SEGMENT_G; + constant DIGIT_C : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_E or SEGMENT_D; + constant DIGIT_D : std_logic_vector(0 to 6) := SEGMENT_B or SEGMENT_G or SEGMENT_E or SEGMENT_D or SEGMENT_C; + constant DIGIT_E : std_logic_vector(0 to 6) := DIGIT_C or SEGMENT_G; + constant DIGIT_F : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_E or SEGMENT_G; + constant DIGIT_MINUS : std_logic_vector(0 to 6) := SEGMENT_G; + constant DIGIT_CLEAR : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_C or SEGMENT_D or SEGMENT_E or SEGMENT_F or SEGMENT_G; + + subtype sseg_digit is std_logic_vector(4 downto 0); + + type sseg_state_rec is record + digit0 : std_logic_vector(0 to 6); + digit1 : std_logic_vector(0 to 6); + digit2 : std_logic_vector(0 to 6); + digit3 : std_logic_vector(0 to 6); + end record; + + function digit_decode(value : sseg_digit) return std_logic_vector; + + component extension_7seg + + generic( + RESET_VALUE : std_logic + ); + port( + --System inputs + sys_clk : in std_logic; + sys_res_n : in std_logic; + -- general extension interface + ext_reg : in extmod_rec; +-- data_out : out gp_register_t; + --Control input +-- val : in std_logic_vector(4 downto 0); +-- pos : in std_logic_vector(1 downto 0); +-- act : std_logic; + --Output + o_digit0 : out std_logic_vector(0 to 6); + o_digit1 : out std_logic_vector(0 to 6); + o_digit2 : out std_logic_vector(0 to 6); + o_digit3 : out std_logic_vector(0 to 6) + ); + end component extension_7seg; + +end extension_7seg_pkg; + +package body extension_7seg_pkg is + + function digit_decode(value : sseg_digit) return std_logic_vector is + + begin + case value is + when "00000" => return DIGIT_0; + when "00001" => return DIGIT_1; + when "00010" => return DIGIT_2; + when "00011" => return DIGIT_3; + when "00100" => return DIGIT_4; + when "00101" => return DIGIT_5; + when "00110" => return DIGIT_6; + when "00111" => return DIGIT_7; + when "01000" => return DIGIT_8; + when "01001" => return DIGIT_9; + when "01010" => return DIGIT_A; + when "01011" => return DIGIT_B; + when "01100" => return DIGIT_C; + when "01101" => return DIGIT_D; + when "01110" => return DIGIT_E; + when "01111" => return DIGIT_F; + when "10000" => return "1111111"; + --when "11111" => return DIGIT_MINUS; + when OTHERS => return DIGIT_CLEAR; + end case; + + end function digit_decode; + +end extension_7seg_pkg; diff --git a/cpu/src/rom.vhd b/cpu/src/rom.vhd new file mode 100644 index 0000000..7de1beb --- /dev/null +++ b/cpu/src/rom.vhd @@ -0,0 +1,23 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity rom is + generic ( + ADDR_WIDTH : integer range 1 to integer'high; + DATA_WIDTH : integer range 1 to integer'high + ); + port( + --System inputs + clk : in std_logic; + --Input + wr_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0); + + wr_en : in std_logic; + data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); + + --Output + data_out : out std_logic_vector(DATA_WIDTH-1 downto 0) + ); + +end entity rom; diff --git a/cpu/src/rom_b.vhd b/cpu/src/rom_b.vhd new file mode 100644 index 0000000..d234e43 --- /dev/null +++ b/cpu/src/rom_b.vhd @@ -0,0 +1,83 @@ +library ieee; + +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.mem_pkg.all; + +architecture behaviour of rom is + + subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0); + type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE; + + -- r0 = 0, r1 = 1, r2 = 3, r3 = A + + signal rrrr_addr : std_logic_vector(31 downto 0); + + signal ram : RAM_TYPE := ( + + + + others => x"F0000000"); + +begin + process(clk) + begin + if rising_edge(clk) then +-- data_out <= ram(to_integer(UNSIGNED(rd_addr))); + + + case rrrr_addr(10 downto 0) is + + when "00000000000" => data_out <= "11101101000000000000000000000000"; -- + when "00000000001" => data_out <= "11101101001000000000000000000000"; -- + when "00000000010" => data_out <= "11100111101000000000000000000000"; -- + + when "00000000011" => data_out <= "11100001000000000000000000100001"; -- + when "00000000100" => data_out <= "11101100100000000000001100000000"; -- + when "00000000101" => data_out <= "00001011011111111111111010000011"; -- + + when "00000000110" => data_out <= "11101101000000000000000000001000"; -- + when "00000000111" => data_out <= "11100111100000000000000000001111"; -- + when "00000001000" => data_out <= "11100111100000000000000000010011"; -- -- + + + when "00000001001" => data_out <= x"ed080080"; --x"ed080048"; -- + when "00000001010" => data_out <= x"ed500080"; -- + when "00000001011" => data_out <= x"fd500002"; -- + when "00000001100" => data_out <= x"eb000107"; + when "00000001101" => data_out <= "11101011000000000000011010000010"; --"11101011000000000000000000000010"; + + when "00000001110" => data_out <= x"e5088800"; + when "00000001111" => data_out <= x"e0150800"; + when "00000010000" => data_out <= x"e7010000"; + when "00000010001" => data_out <= x"ec800000"; + when "00000010010" => data_out <= x"0b000008"; + when "00000010011" => data_out <= x"e1910020"; + when "00000010100" => data_out <= x"eb7ffe07"; + when "00000010101" => data_out <= x"e7197ffc"; + when "00000010110" => data_out <= x"e0018000"; + + when "00000010111" => data_out <= x"e1110020"; + when "00000011000" => data_out <= x"e7810000"; + when "00000011001" => data_out <= x"eb00000a"; + + + when "00000011010" => data_out <= x"ed290080"; + when "00000011011" => data_out <= x"e1080000"; + + when "00000011100" => data_out <= x"e78a8000"; + + when others => data_out <= "11101011000000000000000000000010"; + + end case; + + if wr_en = '1' then + ram(to_integer(UNSIGNED(wr_addr))) <= data_in; + end if; + end if; + end process; + + rrrr_addr(10 downto 0) <= rd_addr; + rrrr_addr(31 downto 11) <= (others => '0'); +end architecture behaviour;