From: Bernhard Urban Date: Wed, 12 Jan 2011 09:06:05 +0000 (+0100) Subject: progs: .sim target hinzugefuegt X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=calu.git;a=commitdiff_plain;h=7bd87d5c82d7b1f7e86a15b0e6f1940020c87330 progs: .sim target hinzugefuegt ... um komfortabler zu sim'en :) --- diff --git a/progs/.gitignore b/progs/.gitignore index 7cc478c..b383360 100644 --- a/progs/.gitignore +++ b/progs/.gitignore @@ -1,2 +1,4 @@ -*.s_prae +*.s_pre *.dthex +*.s_pre_sim +*.dthex_sim diff --git a/progs/Makefile b/progs/Makefile index 8d2675b..8053fc5 100644 --- a/progs/Makefile +++ b/progs/Makefile @@ -26,6 +26,19 @@ fibmmem.prog: @echo " PROG $<" ../tools/dtprog.py $< $(DPROGFLAGS) +%.s_pre_sim: %.s dt_inc.s + @echo " PRESIM $<" + gcc -x c -E -C -P -DDTSIM $< > $@ + +%.dthex_sim: %.s_pre_sim + @echo " ASMSIM $<" + ../3a_asm/dtas < $< > $@ + +fibmmem.sim: +%.sim: %.dthex_sim + @echo " SIM $<" + cd ../3b_sim/; ./sim -f ../progs/$< + .PHONY: clean clean: - rm -rf *.dthex *.s_pre + rm -rf *.dthex *.s_pre *.dthex_sim *.s_pre_sim diff --git a/progs/dt_inc.s b/progs/dt_inc.s index 39b8c31..adedc50 100644 --- a/progs/dt_inc.s +++ b/progs/dt_inc.s @@ -23,21 +23,28 @@ int2hex: .define UART_RECV_NEW, 0x2 u_recv_byte: +#ifndef DTSIM ldw r3, UART_STATUS(r10) andx r3, UART_RECV_NEW brzs+ u_recv_byte; branch if zero xor r0, r0, r0 ldw r0, UART_RECV(r10) +#else + ldis r0, 0x41 ; 'A' +#endif ret u_send_byte: +#ifndef DTSIM ldw r9, UART_STATUS(r10) andx r9, UART_TRANS_EMPTY brnz+ u_send_byte ; branch if not zero stb r1, UART_TRANS(r10) +#endif ret u_send_uint: +#ifndef DTSIM addi r8, r1, 0 ;usb_sendbuffersafe ("0x", 2); xor r1, r1, r1 @@ -65,8 +72,12 @@ u_send_uint_loop: lls r8, r8, 4 addi r7, r7, 1 br u_send_uint_loop +#else + ret +#endif u_send_string: +#ifndef DTSIM ; r1 = addr ; r2 = len addi r3, r1, 0 @@ -78,17 +89,24 @@ u_send_string_int: addis r2, r2, 0-1 addi r3, r3, 1 br u_send_string_int +#else + ret +#endif u_send_newline: +#ifndef DTSIM xor r1, r1, r1 ldi r1, 0x0a call u_send_byte ldi r1, 0x0d call u_send_byte +#endif ret u_init: +#ifndef DTSIM xor r10, r10, r10 ldi r10, UART_BASE@lo ldih r10, UART_BASE@hi +#endif ret