From: Stefan Rebernig <stefan.rebernig@gmail.com>
Date: Sat, 11 Dec 2010 11:23:13 +0000 (+0100)
Subject: return - erster versuch
X-Git-Tag: bootrom_v1~90
X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=calu.git;a=commitdiff_plain;h=2d083a4b629d92d29b08deef86def56633866f31

return - erster versuch
---

diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd
index ae69be8..6537555 100644
--- a/cpu/src/decoder_b.vhd
+++ b/cpu/src/decoder_b.vhd
@@ -317,7 +317,12 @@ begin
 		--	instr_s.op_detail(RET_OPT) := '0';
 		end if;
 
-		if (instr_s.predicates = "1111") then
+		if (instr_s.jmptype = "10") then
+			instr_s.op_group := JMP_ST_OP;
+			instr_s.op_detail(RET_OPT) := '1';
+		end if;
+
+		if (instr_s.predicates = "1111" or instr_s.jmptype = "10") then
 			instr_s.bp := '0';
 		end if;
 	end if;
diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 694194f..0dbf3d4 100644
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -12,7 +12,7 @@ architecture behaviour of r_w_ram is
 	
 									-- r0 = 0, r1 = 1, r2 = 3, r3 = A
 
-	signal ram : RAM_TYPE := (  0 => "11101101000000000000000000000000", -- r0 = 0
+	signal ram : RAM_TYPE := (  0 => "11101011000000000000000000010111", -- call +1
 
 				    1 => "11101101000010000000000000111000", -- r1 = 7
 				    2 => "11101101000100000000000000101000", -- r2 = 5
@@ -20,23 +20,48 @@ architecture behaviour of r_w_ram is
 				    4 => "11100000001000010001100000000000", -- r4 = r2 + r3
 				    5 => "11100010001010100000100000000000", -- r5 = r4 and r1
 
-				    6 => "11100001000000000000000000001000", -- r0 = r0 + 1
-				    7 => "11101100100000000000000000011000", -- cmpi r0 , 2      
+				    6 => "11101011000000000000000000001011", -- r0 = r0 + 1
+--				    7 => "11101100100000000000000000011000", -- cmpi r0 , 2      
 
-				    8 => "00001011011111111111110010000111", -- jump -7
-				    9 => "11101011000000000000000010000010", -- jump +1
+				    7 => "00001011011111111111110010000111", -- jump -7
+				    8 => "11101011000000000000000010000010", -- jump +1
 				   --10 => "11101011000000000000000010000010", -- jump +1
 
-                                   10 => "11100111101010100000000000000001", -- stw r5,r4,1
-			 	   11 => "11101100001000100000000000000000", -- cmp r4 , r4       => 2-2 => 1001
+                                   9 => "11100111101010100000000000000001", -- stw r5,r4,1
+			 	   10 => "11101100001000100000000000000000", -- cmp r4 , r4       => 2-2 => 1001
 
-				   12 => "11101011000000000000000000000010", -- jump +0
+				   11 => "11101011000000000000000000000010", -- jump +0
 
 				   
 
 
 				  others => x"F0000000");
 
+--	signal ram : RAM_TYPE := (  0 => "11101101000000000000000000000000", -- r0 = 0
+--
+--				    1 => "11101101000010000000000000111000", -- r1 = 7
+--				    2 => "11101101000100000000000000101000", -- r2 = 5
+--				    3 => "11101101000110000000000000100000", -- r3 = 4
+--				    4 => "11100000001000010001100000000000", -- r4 = r2 + r3
+--				    5 => "11100010001010100000100000000000", -- r5 = r4 and r1
+--
+--				    6 => "11100001000000000000000000001000", -- r0 = r0 + 1
+--				    7 => "11101100100000000000000000011000", -- cmpi r0 , 2      
+--
+--				    8 => "00001011011111111111110010000111", -- jump -7
+--				    9 => "11101011000000000000000010000010", -- jump +1
+--				   --10 => "11101011000000000000000010000010", -- jump +1
+--
+  --                                 10 => "11100111101010100000000000000001", -- stw r5,r4,1
+	--		 	   11 => "11101100001000100000000000000000", -- cmp r4 , r4       => 2-2 => 1001
+--
+--				   12 => "11101011000000000000000000000010", -- jump +0
+
+				   
+
+
+--				  others => x"F0000000");
+
 --	signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0    => r2 = 1
 --				    1 => "11100000000110001000000000000000", --add r3, r1, r0    => r3 = 1
 --				    2 => "11100000001000011001000000000000", --add r4, r3, r2    => r4 = 2
diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 862c1d3..5123f76 100644
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -98,14 +98,19 @@ begin
 	--jump <= (alu_jmp xor br_pred) and (write_en or wb_reg.dmem_en);
 	jump <= (alu_jmp xor br_pred);-- and (write_en or wb_reg.dmem_en);
 
+	if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
+		jump_addr <= data_ram_read;
+	else
+		jump_addr <= result;	
+	end if;
+
 --	if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
 --		jump <= '1';
 --	end if;
 
-	jump_addr <= result;
-	if ((alu_jmp and wb_reg.dmem_en) = '1') then
-		jump_addr <= data_ram_read;
-	end if;
+--	if ((alu_jmp and wb_reg.dmem_en) = '1') then
+--		jump_addr <= data_ram_read;
+--	end if;
 
 end process;