From: Martin Perner Date: Wed, 19 Jan 2011 18:33:22 +0000 (+0100) Subject: DSE version X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=calu.git;a=commitdiff_plain;h=1d5de476f5439321494c00fe329ad6369e547cef DSE version --- diff --git a/dt/.gitignore b/dt/.gitignore index 2429abe..ded9352 100644 --- a/dt/.gitignore +++ b/dt/.gitignore @@ -7,7 +7,7 @@ work/ *.pof *.rbf *.sof -dt.*.rpt -dt.*.summary +*.rpt +*.summary output_file.pof output_file.rbf diff --git a/dt/DSE.qsf b/dt/DSE.qsf new file mode 100644 index 0000000..00be9e8 --- /dev/null +++ b/dt/DSE.qsf @@ -0,0 +1,153 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2010 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition +# Date created = 15:08:54 December 16, 2010 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# DSE3_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY Cyclone +set_global_assignment -name DEVICE EP1C12Q240C8 +set_global_assignment -name TOP_LEVEL_ENTITY core_top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:17:41 JANUARY 19, 2011" +set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_location_assignment PIN_178 -to bus_tx +set_location_assignment PIN_153 -to bus_rx +set_location_assignment PIN_166 -to led2 +set_location_assignment PIN_42 -to sys_res +set_location_assignment PIN_41 -to soft_res +set_location_assignment PIN_152 -to sys_clk_in + +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" + + +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name ENABLE_DRC_SETTINGS ON +set_global_assignment -name ENABLE_CLOCK_LATENCY ON +set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM +set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +set_global_assignment -name MUX_RESTRUCTURE OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name FMAX_REQUIREMENT "50 MHz" + +set_global_assignment -name MISC_FILE ./dt.dpf + + +set_global_assignment -name VHDL_FILE pll/pll.vhd + + +set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_be_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_be.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/rom.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/rom_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx_arc.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx_arc.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/mem_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_imp_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_imp_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_imp.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_interrupt_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_interrupt.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_timer_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_timer_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_timer.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/extension.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/exec_op.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/decoder_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/decoder.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/core_top.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/core_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/common_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/alu_pkg.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/alu_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/alu.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/xor_op_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/shift_op_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/or_op_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd +set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd + +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 3.0 +set_global_assignment -name SEED 22 +set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name DO_COMBINED_ANALYSIS ON +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/dt/DSE.sdc b/dt/DSE.sdc new file mode 100644 index 0000000..229d30b --- /dev/null +++ b/dt/DSE.sdc @@ -0,0 +1,71 @@ +########################################################################### +# +# Generated by : Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition +# +# Project : dt +# Revision : dt +# +# Date : Thu Jan 13 17:54:53 CET 2011 +# +########################################################################### + + +# +# ------------------------------------------ +# +# Create generated clocks based on PLLs +derive_pll_clocks -use_tan_name +# +# ------------------------------------------ +# WARNING: Global Fmax translated to derive_clocks. Behavior is not identical +if {![info exist ::qsta_message_posted]} { + post_message -type warning "Original Global Fmax translated from QSF using derive_clocks" + set ::qsta_message_posted 1 +} +derive_clocks -period "50 MHz" +# + + +# Original Clock Setting Name: sys_clk +create_clock -period "20.000 ns" \ + -name {sys_clk} {sys_clk} +# --------------------------------------------- + +# ** Clock Latency +# ------------- + +# ** Clock Uncertainty +# ----------------- + +# ** Multicycles +# ----------- +# ** Cuts +# ---- + +# ** Input/Output Delays +# ------------------- + + + + +# ** Tpd requirements +# ---------------- + +# ** Setup/Hold Relationships +# ------------------------ + +# ** Tsu/Th requirements +# ------------------- + + +# ** Tco/MinTco requirements +# ----------------------- + +# +# Entity Specific Timing Assignments found in +# the Timing Analyzer Settings report panel +# + + +# --------------------------------------------- + diff --git a/dt/dt.qpf b/dt/dt.qpf index e7fbff1..f311d83 100644 --- a/dt/dt.qpf +++ b/dt/dt.qpf @@ -18,12 +18,12 @@ # # Quartus II # Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition -# Date created = 12:37:50 January 18, 2011 +# Date created = 15:17:41 January 19, 2011 # # -------------------------------------------------------------------------- # QUARTUS_VERSION = "10.0" -DATE = "12:37:50 January 18, 2011" +DATE = "15:17:41 January 19, 2011" # Revisions