From: Stefan Rebernig <stefan.rebernig@gmail.com>
Date: Sat, 11 Dec 2010 14:33:56 +0000 (+0100)
Subject: fib 1
X-Git-Tag: bootrom_v1~84
X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=calu.git;a=commitdiff_plain;h=0c7231e471031c7d03f241dc4970b622fc64c695

fib 1
---

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index c77feb0..321364e 100644
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -70,6 +70,7 @@ add wave  -radix hexadecimal /pipeline_tb/exec_st/gpmp_inst/psw
 
 add wave  -radix hexadecimal /pipeline_tb/addr_pin
 add wave  -radix hexadecimal /pipeline_tb/data_pin
+add wave  -radix hexadecimal /pipeline_tb/writeback_st/data_ram_read
 add wave  -radix hexadecimal /pipeline_tb/dmem_wr_en_pin
 
 run 5000 ns
diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd
index 60cc287..9bd9d81 100644
--- a/cpu/src/decode_stage_b.vhd
+++ b/cpu/src/decode_stage_b.vhd
@@ -163,7 +163,7 @@ begin
 	rtw_rec_nxt.reg1_addr <= instr_spl.reg_src1_addr;
 	rtw_rec_nxt.reg2_addr <= instr_spl.reg_src2_addr;
 
-	if (instr_spl.op_detail(IMM_OPT) = '1') then
+	if (instr_spl.op_detail(IMM_OPT) = '1') then -- or instr_spl.op_group = LDST_OP
 		rtw_rec_nxt.immediate <= instr_spl.immediate;
 		rtw_rec_nxt.imm_set <= '1';
 	end if;
diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 204479e..1bbf460 100644
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -13,11 +13,19 @@ architecture behaviour of r_w_ram is
 									-- r0 = 0, r1 = 1, r2 = 3, r3 = A
 
 	signal ram : RAM_TYPE := (
-0 => x"ed080048",	--;ldi r1, 9;;
-1 => x"ed500080",	--;ldil r10, list@lo ;; global pointer
-2 => x"fd500002",	--;ldih r10, list@hi;;
-3 => x"eb000107",	--;call+ fibcall;;
-4 => x"eb7ffe03",	--;br+ main;;
+
+	0 => "11101101000000000000000000000000",
+	1 => "11101101001000000000000000000000",
+	2 => "11100111101000000000000000000000",
+	3 => "11100001000000000000000000100001",
+	4 => "11101100100000000000010000000000",
+	5 => "00001011011111111111111010000011",
+
+6 => x"ed080048",	--;ldi r1, 9;;
+7 => x"ed500080",	--;ldil r10, list@lo ;; global pointer
+8 => x"fd500002",	--;ldih r10, list@hi;;
+9 => x"eb000107",	--;call+ fibcall;;
+10 => x"eb7ffe03",	--;br+ main;;
 		--2; fib(n) {
 		--2;   if (list[n] > 0) {
 		--2;   	return list[n]
@@ -28,32 +36,32 @@ architecture behaviour of r_w_ram is
 		--2; }
 		--3;fibcall;
 		--2;update counter for aligned access
-5 => x"e5088800",	--;lls r1, r1, 2 ;; *4
+11 => x"e5088800",	--;lls r1, r1, 2 ;; *4
 		--2;calculate adress of top element
-6 => x"e0150800",	--;add r2, r10, r1;;
+12 => x"e0150800",	--;add r2, r10, r1;;
 		--3;fibmem;
 		--2;load top element
-7 => x"e7010000",	--;ldw r0, 0(r2);;
+13 => x"e7010000",	--;ldw r0, 0(r2);;
 		--2;compare if set
-8 => x"ec800000",	--;cmpi r0, 0;;
+14 => x"ec800000",	--;cmpi r0, 0;;
 		--2;return if set
-9 => x"0b000008",	--;retnz-;;
+15 => x"0b000008",	--;retnz-;;
 		--2;decrement adress for next lopp
-10 => x"e1910020",	--;subi r2, r2, 4;;
+16 => x"e1910020",	--;subi r2, r2, 4;;
 		--2;iterative call for n-1 element
-11 => x"eb7ffe07",	--;call+ fibmem;;
+17 => x"eb7ffe07",	--;call+ fibmem;;
 		--2;load n-2 element
-12 => x"e7197ffc",	--;ldw r3, 0-4(r2);;
+18 => x"e7197ffc",	--;ldw r3, 0-4(r2);;
 		--2;add n-1 and n-2 element
-13 => x"e0018000",	--;add r0, r3, r0;;
+19 => x"e0018000",	--;add r0, r3, r0;;
 		--2;increment address for n element
 		--2;is needed because after return
 		--2;we need r2 to be set to the address
 		--2;of element n
-14 => x"e1110020",	--;addi r2, r2, 4;;
+20 => x"e1110020",	--;addi r2, r2, 4;;
 		--2;store fib n
-15 => x"e7810000",	--;stw r0, 0(r2);;
-16 => x"eb00000a",	--;ret+;;
+21 => x"e7810000",	--;stw r0, 0(r2);;
+22 => x"eb00000a",	--;ret+;;