register branch (untested) + de1 top level fix

diff --git a/cpu/src/core_top_c2de1.vhd b/cpu/src/core_top_c2de1.vhd
index ba810a89659021d2e63cf9feb410dc15cb07a835..b7410012b48a1010eeaafc5892d77ef792c2824f 100644 (file)
--- a/cpu/src/core_top_c2de1.vhd
+++ b/cpu/src/core_top_c2de1.vhd
@@ -45,20 +45,17 @@ architecture behav of core_top_c2de1 is
                signal reg_we_pin : std_logic;
                signal to_next_stage : dec_op;
 
---             signal reg1_rd_data_pin : gp_register_t;
---             signal reg2_rd_data_pin : gp_register_t;
-
-                 signal result_pin : gp_register_t;--reg
-                 signal result_addr_pin : gp_addr_t;--reg
-                 signal addr_pin : word_t; --memaddr
-                 signal data_pin : gp_register_t; --mem data --ureg
-                 signal alu_jump_pin : std_logic;--reg
-                 signal brpr_pin  : std_logic;  --reg
-                 signal wr_en_pin : std_logic;--regop --reg
-                 signal dmem_pin  : std_logic;--memop
-                 signal dmem_wr_en_pin : std_logic;
-                 signal hword_pin  : std_logic;
-                 signal byte_s_pin : std_logic;
+      signal result_pin : gp_register_t;--reg
+      signal result_addr_pin : gp_addr_t;--reg
+      signal addr_pin : word_t; --memaddr
+      signal data_pin : gp_register_t; --mem data --ureg
+      signal alu_jump_pin : std_logic;--reg
+      signal brpr_pin  : std_logic;  --reg
+      signal wr_en_pin : std_logic;--regop --reg
+      signal dmem_pin  : std_logic;--memop
+      signal dmem_wr_en_pin : std_logic;
+      signal hword_pin  : std_logic;
+      signal byte_s_pin : std_logic;
                                 
                 signal gpm_in_pin : extmod_rec;
                 signal gpm_out_pin : gp_register_t;
@@ -79,7 +76,7 @@ begin
        fetch_st : fetch_stage
                generic map (
        
-                       '0',
+                       RESET_VALUE,
                        '1'
                )
                
@@ -107,7 +104,7 @@ begin
        decode_st : decode_stage
                generic map (
                        -- active reset value
-                       '0',
+                       RESET_VALUE,
                        -- active logic value
                        '1'
                        
@@ -132,62 +129,51 @@ begin
                );
 
           exec_st : execute_stage
-                generic map('0')
+                generic map(RESET_VALUE)
                 port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
 
-                       vers_nxt.result <= result_pin;
-                       vers_nxt.result_addr <= result_addr_pin;
-                       vers_nxt.address <= addr_pin;
-                       vers_nxt.ram_data <= data_pin;
-                       vers_nxt.alu_jmp <= alu_jump_pin;
-                       vers_nxt.br_pred <= brpr_pin;
-                       vers_nxt.write_en <= wr_en_pin;
-                       vers_nxt.dmem_en <= dmem_pin;
-                       vers_nxt.dmem_write_en <= dmem_wr_en_pin;
-                       vers_nxt.hword <= hword_pin;
-                       vers_nxt.byte_s <= byte_s_pin;
+--                     vers_nxt.result <= result_pin;
+--                     vers_nxt.result_addr <= result_addr_pin;
+--                     vers_nxt.address <= addr_pin;
+--                     vers_nxt.ram_data <= data_pin;
+--                     vers_nxt.alu_jmp <= alu_jump_pin;
+--                     vers_nxt.br_pred <= brpr_pin;
+--                     vers_nxt.write_en <= wr_en_pin;
+--                     vers_nxt.dmem_en <= dmem_pin;
+--                     vers_nxt.dmem_write_en <= dmem_wr_en_pin;
+--                     vers_nxt.hword <= hword_pin;
+--                     vers_nxt.byte_s <= byte_s_pin;
                                                                         
---          writeback_st : writeback_stage
---                generic map('0', '1')
---                port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
---                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
---                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
+          writeback_st : writeback_stage
+                generic map(RESET_VALUE, '1', "altera")
+                port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
+                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, 
+                                        new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req);
+
+
+--                     writeback_st : writeback_stage
+--                generic map(RESET_VALUE, '1', "altera")
+--                port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
+--                vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
+--                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
+--                             -- instruction memory program port :D
+--                             new_im_data, im_addr, im_data,
+--                             sseg0, sseg1, sseg2, sseg3, int_req);
 --
 
-                       writeback_st : writeback_stage
-                generic map('0', '1', "altera")
-                port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
-                vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
-                               -- instruction memory program port :D
-                               new_im_data, im_addr, im_data,
-                               sseg0, sseg1, sseg2, sseg3, int_req);
-
-
 syn: process(sys_clk, sys_res)
 
 begin
 
-       if sys_res = '1' then
---                     vers.result <= (others => '0');
---                     vers.result_addr <= (others => '0');
---                     vers.address <= (others => '0');
---                     vers.ram_data <= (others => '0');
---                     vers.alu_jmp <= '0';
---                     vers.br_pred <= '0';
---                     vers.write_en <= '0';
---                     vers.dmem_en <= '0';
---                     vers.dmem_write_en <= '0';
---                     vers.hword <= '0';
---                     vers.byte_s <= '0';
+       if sys_res = RESET_VALUE then
        
-               sync <= (others => '0');
+               sync <= (others => RESET_VALUE);
        
        elsif rising_edge(sys_clk) then
---             vers <= vers_nxt;
-                       sync(1) <= not sys_res;
+                       sync(1) <= sys_res;
                        for i in 2 to SYNC_STAGES loop
                                sync(i) <= sync(i - 1);
                        end loop;
@@ -197,24 +183,7 @@ begin
 end process;
 
 sys_res_n <= sync(SYNC_STAGES);
-       
---init : process(all)
-
---begin
---     jump_result_pin <= (others => '0');
---     alu_jump_bit_pin <= '0';
---     reg_w_addr_pin <= (others => '0');
---     reg_wr_data_pin <= (others => '0');
---     reg_we_pin <= '0';
-       
---end process;
-       
---     result <= result_pin;
-       nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
-
-       jump_result <= prog_cnt_pin; --jump_result_pin;
---     sys_res <= '1';
-
---     reg_wr_data <= reg_wr_data_pin;
+nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
+jump_result <= prog_cnt_pin; --jump_result_pin;
 
 end behav;

diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd
index c51e1318ba0ee63d474a5c6799895234c3cb03a8..525d408170a0b6b5bca6b12cfe42ec07f85df0e1 100644 (file)
--- a/cpu/src/decoder_b.vhd
+++ b/cpu/src/decoder_b.vhd
@@ -369,20 +369,47 @@ begin
                        instr_s.immediate(31 downto 16) := (others => '1');
                end if;
 
-               if (instr_s.jmptype = "00") then
---                     instr_s.op_detail(SUB_OPT) := not instr_s.opcode(0);
-                       instr_s.op_group := JMP_OP;
-               end if;
+               case instr_s.jmptype is 
+                       when "00" =>
+                               instr_s.op_group := JMP_OP;
+                       
+                       when "01" =>
+                               instr_s.op_group := JMP_ST_OP;
+                       
+                       when "10" =>
+                               instr_s.op_group := JMP_ST_OP;
+                               instr_s.op_detail(RET_OPT) := '1';
+                       
+                       when "11" =>
+                               instr_s.op_group := JMP_OP;
+                               instr_s.op_detail(JMP_REG_OPT) := '1';
+                               instr_s.op_detail(IMM_OPT) := '1';
+                               instr_s.immediate := (others => '0');
+                       
+                       when others => null;
+               end case;
                
-               if (instr_s.jmptype = "01") then
-                       instr_s.op_group := JMP_ST_OP;
-               --      instr_s.op_detail(RET_OPT) := '0';
-               end if;
-
-               if (instr_s.jmptype = "10") then
-                       instr_s.op_group := JMP_ST_OP;
-                       instr_s.op_detail(RET_OPT) := '1';
-               end if;
+--             if (instr_s.jmptype = "00") then
+----                   instr_s.op_detail(SUB_OPT) := not instr_s.opcode(0);
+--                     instr_s.op_group := JMP_OP;
+--             end if;
+--             
+--             if (instr_s.jmptype = "01") then
+--                     instr_s.op_group := JMP_ST_OP;
+--             --      instr_s.op_detail(RET_OPT) := '0';
+--             end if;
+--
+--             if (instr_s.jmptype = "10") then
+--                     instr_s.op_group := JMP_ST_OP;
+--                     instr_s.op_detail(RET_OPT) := '1';
+--             end if;
+--             
+--             if (instr_s.jmptype = "11") then
+--                     instr_s.op_group := JMP_OP;
+--                     instr_s.op_detail(JMP_REG_OPT) := '1';
+--                     instr_s.op_detail(IMM_OPT) := '1';
+--                     instr_s.immediate := (others => '0');
+--             end if;
 
                if (instr_s.predicates = "1111" or instr_s.jmptype = "10") then
                        instr_s.bp := '0';

diff --git a/cpu/src/rs232_tx_arc.vhd b/cpu/src/rs232_tx_arc.vhd
index 3dce8796b52fb5163c16dfa296c542fa49ecce19..1caa47dc5e4b975dce2dc6033ed3843e1bb4c526 100755 (executable)
--- a/cpu/src/rs232_tx_arc.vhd
+++ b/cpu/src/rs232_tx_arc.vhd
@@ -23,7 +23,7 @@ architecture beh of rs232_tx is
        type STATE_TYPE is (IDLE,SEND);
        signal state, state_next : STATE_TYPE;
        signal bus_tx_int, bus_tx_nxt : std_logic := '1';
-       signal baud_cnt,baud_cnt_next : integer;
+       signal baud_cnt,baud_cnt_next : integer := 0;
        signal cnt, cnt_next : natural range 0 to 11 := 0;
        signal idle_sig, idle_sig_next : std_logic := '0';