X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=calu.git;a=blobdiff_plain;f=cpu%2Fsrc%2Fwriteback_stage_b.vhd;fp=cpu%2Fsrc%2Fwriteback_stage_b.vhd;h=6a3a4e6c0e11ef5b500e29f9ba24e5ed698d9c40;hp=acf0f7db2032a88263d11df7b924e9aeac5450a5;hb=0ba0c7effbaf554ad42db51334581859a0570bfa;hpb=1c926aa503f06fc7844b6482c89b55961a58d16b

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index acf0f7d..6a3a4e6 100755
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -234,7 +234,7 @@ begin
 	if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
 		jump_addr <= data_ram_read;
 	else
-		jump_addr <= result;	
+		jump_addr <= result;
 	end if;
 
 --	if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
@@ -269,7 +269,7 @@ begin
 	data_addr <= (others => '0');
 	dmem_we <= '0';
 	
-	if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then
+	if (wb_reg.address(DATA_ADDR_WIDTH+3) /= '1') then
 		data_out := data_ram_read;
 	else
 		reg_we_v := reg_we_v and ext_anysel;
@@ -306,7 +306,7 @@ begin
 	
 	data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length); 
 	
-	if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
+	if (wb_reg_nxt.address(DATA_ADDR_WIDTH+3) /= '1') then
 		data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
 		dmem_we <= wb_reg_nxt.dmem_write_en;
 	end if;