X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=calu.git;a=blobdiff_plain;f=cpu%2Fsrc%2Fcore_top_s3e.vhd;h=62b2b5d7f69f4ddbb90ee1ac8cb2784453b3c9d0;hp=dd3791ba6cd00d3f8e30f7fd44a278e030a1bc43;hb=02fa510d7e698977a9fd175180f8994e2ba6ee95;hpb=b3f109c2f4edf52bc4071f9f8d71d868fb117c00

diff --git a/cpu/src/core_top_s3e.vhd b/cpu/src/core_top_s3e.vhd
index dd3791b..62b2b5d 100644
--- a/cpu/src/core_top_s3e.vhd
+++ b/cpu/src/core_top_s3e.vhd
@@ -11,6 +11,7 @@ entity core_top is
 	port(
 		--System input pins
 		   sys_res : in std_logic;
+			soft_res : in std_logic;
 			sys_clk : in std_logic;
 --			result : out gp_register_t;
 --			reg_wr_data : out gp_register_t
@@ -65,8 +66,9 @@ architecture behav of core_top is
 		 signal gpm_out_pin : gp_register_t;
 		 signal nop_pin : std_logic;
 		 
-		 signal sync : std_logic_vector(1 to SYNC_STAGES);
-		 signal sys_res_n : std_logic;
+		 signal sync, sync2 : std_logic_vector(1 to SYNC_STAGES);
+		 signal sys_res_n, soft_res_n : std_logic;
+		 signal xilinxfail : std_logic;
 
 		 signal int_req : interrupt_t;
 
@@ -87,7 +89,7 @@ begin
 		--System inputs
 			clk => sys_clk, --: in std_logic;
 			reset => sys_res_n, --: in std_logic;
-		
+			s_reset => soft_res_n,
 		--Data inputs
 			jump_result => jump_result_pin, --: in instruction_addr_t;
 			prediction_result => prediction_result_pin, --: in instruction_addr_t;
@@ -115,7 +117,7 @@ begin
 		port map (
 		--System inputs
 			clk => sys_clk, --: in std_logic;
-			reset => sys_res_n, -- : in std_logic;
+			reset => xilinxfail, -- : in std_logic;
 
 		--Data inputs
 			instruction => instruction_pin, --: in instruction_word_t;
@@ -133,7 +135,7 @@ begin
 
           exec_st : execute_stage
                 generic map('0')
-                port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+                port map(sys_clk, xilinxfail,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
 
@@ -157,8 +159,8 @@ begin
 --
 
 			writeback_st : writeback_stage
-                generic map('0', '1', "s3e")
-                port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
+                generic map('0', '1', "s3e", 434)
+                port map(sys_clk, xilinxfail, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
 				-- instruction memory program port :D
@@ -185,6 +187,7 @@ begin
 --			vers.byte_s <= '0';
 	
 		sync <= (others => '0');
+		sync2 <= (others => '0');
 	
 	elsif rising_edge(sys_clk) then
 		led1 <= '1';
@@ -193,12 +196,17 @@ begin
 			for i in 2 to SYNC_STAGES loop
 				sync(i) <= sync(i - 1);
 			end loop;
-				
+			sync2(1) <= not soft_res;
+			for i in 2 to SYNC_STAGES loop
+				sync2(i) <= sync2(i - 1);
+			end loop;
 	end if;
 	
 end process;
 
 sys_res_n <= sync(SYNC_STAGES);
+soft_res_n <= sync2(SYNC_STAGES);
+xilinxfail <= sys_res_n and soft_res_n;
 	
 --init : process(all)