X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=calu.git;a=blobdiff_plain;f=cpu%2Fsrc%2Fcore_top.vhd;fp=cpu%2Fsrc%2Fcore_top.vhd;h=f5354e33f4d5f9f0cf4a0dc130a07793830c24e6;hp=f3e132328db24cfdc16516be3954a6a24673f47a;hb=f93d3c8cdbed65c78214fde28f12c55d0e8232a5;hpb=0ba0c7effbaf554ad42db51334581859a0570bfa

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index f3e1323..f5354e3 100644
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -12,7 +12,7 @@ entity core_top is
 		--System input pins
 		   sys_res : in std_logic;
 			soft_res : in std_logic;
-			sys_clk : in std_logic;
+			sys_clk_in : in std_logic;
 --			result : out gp_register_t;
 --			reg_wr_data : out gp_register_t
 		  -- uart
@@ -33,6 +33,8 @@ architecture behav of core_top is
 		constant SYNC_STAGES : integer := 2;
 		constant RESET_VALUE : std_logic := '0';
 
+		signal sys_clk : std_logic;
+
 		signal jump_result : instruction_addr_t;
 		signal jump_result_pin : instruction_addr_t;
 		signal prediction_result_pin : instruction_addr_t;
@@ -74,8 +76,23 @@ architecture behav of core_top is
 		 signal im_addr, im_data : gp_register_t;
 		 
 		 signal vers, vers_nxt : exec2wb_rec;
+
+
+	component pll
+		PORT
+		(
+			inclk0 : IN STD_LOGIC  := '0';
+			c0	    : OUT STD_LOGIC
+		);
+	end component;
 begin
 
+	pll_inst : pll PORT MAP (
+		inclk0 => sys_clk_in,
+		c0     => sys_clk
+	);
+
+
 	fetch_st : fetch_stage
 		generic map (