#define PROGINSTR stw r0, PDATA(r13)
+#include "dt_inc.s"
.data
.org 0x10
inputdata:
.ifill push r6
.text
- .define UART_BASE, 0x2000
- .define UART_STATUS, 0x0
- .define UART_RECV, 0xc
- .define UART_TRANS, 0x8
-
- .define UART_TRANS_EMPTY, 0x1
- .define UART_RECV_NEW, 0x2
-
- .define PBASE, 0x2030
- .define PADDR, 0x4
- .define PDATA, 0x8
.org 0
start:
- call main
- call main
+ call+ main
+ call+ main
ret
main:
- ldi r10, UART_BASE@lo
- ldih r10, UART_BASE@hi
-;recv byte
-u_recv_byte:
- ldw r3, UART_STATUS(r10)
- andx r3, UART_RECV_NEW
- brzs+ u_recv_byte; branch if zero
-
- ldw r0, UART_RECV(r10)
-;recv byte
- ldis r0, 0x48
-u_test:
- ldw r9, UART_STATUS(r10)
- andx r9, UART_TRANS_EMPTY
- brnz+ u_test ; branch if not zero
- stb r0, UART_TRANS(r10)
+ call+ u_init
+ call+ u_recv_byte
+ ; benchprolog
+ call t_init
+ call t_stop
+ ldis r1, 0
+ call t_valset
+ call t_start
+ ; /benchprolog
;set address of input
ldis r1, inputdata@lo
ldih r1, inputdata@hi
-
;set address of program start
ldis r2, (prog_start/4)@lo
ldih r2, (prog_start/4)@hi
ldis r13, PBASE@lo
ldih r13, PBASE@hi
-
;set programmer address
stw r2, PADDR(r13)
;call jit'ed prog
call+ prog_start
-;send result
+ ; benchepilog
push r0
- ldi r10, UART_BASE@lo
- ldih r10, UART_BASE@hi
-
-u_send_by1:
- ldw r9, UART_STATUS(r10)
- andx r9, UART_TRANS_EMPTY
- brnz+ u_send_by1 ; branch if not zero
- ldis r0, 0x50
- stb r0, UART_TRANS(r10)
-
-u_send_byte:
- ldw r9, UART_STATUS(r10)
- andx r9, UART_TRANS_EMPTY
- brnz+ u_send_byte ; branch if not zero
- pop r0
- stb r0, UART_TRANS(r10)
-
-;send result
+ call+ t_init
+ call+ t_stop
+ call+ t_valget
+ subi r0, r0, 0xd ; offset abziehen
+ pop r3
+ push r0
+ push r3
+ ; /benchepilog
+
+ ;send result
+ call+ u_init
+ pop r1
+ call u_send_byte
+ call u_send_newline
+ pop r1
+ call u_send_uint
+ call u_send_newline
br+ main
br+ vm_loop
-prog_start:
.data
jumptable: