Design Assistant report for dt
-Mon Dec 20 17:39:01 2010
+Mon Dec 20 23:23:39 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+-------------------------------------------------------------------------+
; Design Assistant Summary ;
+-----------------------------------+-------------------------------------+
-; Design Assistant Status ; Analyzed - Mon Dec 20 17:39:01 2010 ;
+; Design Assistant Status ; Analyzed - Mon Dec 20 23:23:39 2010 ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Family ; Cyclone ;
; - Rule S102 ; 12 ;
; Total Medium Violations ; 1 ;
; - Rule R102 ; 1 ;
-; Total Information only Violations ; 99 ;
-; - Rule T101 ; 49 ;
+; Total Information only Violations ; 100 ;
+; - Rule T101 ; 50 ;
; - Rule T102 ; 50 ;
+-----------------------------------+-------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------+---------------------------------------+
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; execute_stage:exec_st|reg.alu_jump ;
; Synchronous and reset port source node(s) list ; sys_res ;
-; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[0] ;
+; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[2] ;
; Synchronous and reset port source node(s) list ; sys_res ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[1] ;
; Synchronous and reset port source node(s) list ; sys_res ;
-; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[2] ;
-; Synchronous and reset port source node(s) list ; sys_res ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[3] ;
; Synchronous and reset port source node(s) list ; sys_res ;
-; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[4] ;
+; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[0] ;
+; Synchronous and reset port source node(s) list ; sys_res ;
+; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[6] ;
; Synchronous and reset port source node(s) list ; sys_res ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[5] ;
; Synchronous and reset port source node(s) list ; sys_res ;
-; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[6] ;
+; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[4] ;
; Synchronous and reset port source node(s) list ; sys_res ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; fetch_stage:fetch_st|instr_r_addr[7] ;
; Synchronous and reset port source node(s) list ; sys_res ;
+-----------------------------------------------------------------------------------------------------------------------+---------------------------------------+
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Medium Violations ;
-+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+
-; Rule name ; Name ;
-+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+
-; Rule R102: External reset signals should be synchronized using two cascaded registers ; sys_res ;
-; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[1] ;
-; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[2] ;
-; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[3] ;
-; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[4] ;
-; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[5] ;
-; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[6] ;
-; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[7] ;
-; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[8] ;
-; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[9] ;
-; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[10] ;
-+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Medium Violations ;
++---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+
+; Rule name ; Name ;
++---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+
+; Rule R102: External reset signals should be synchronized using two cascaded registers ; sys_res ;
+; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[15] ;
+; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[31] ;
+; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[14] ;
+; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[12] ;
+; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[13] ;
+; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[10] ;
+; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[11] ;
+; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[8] ;
+; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[9] ;
+; Reset signal destination node(s) list ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[7] ;
++---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------+
; Rule name ; Name ; Fan-Out ;
+------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------+
-; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[1]~19 ; 96 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.dmem_en ; 63 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|left_operand[5]~3 ; 53 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; sys_res ; 543 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23 ; 63 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; ~GND ; 208 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a1 ; 33 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|left_operand[5]~3 ; 54 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[1]~19 ; 95 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.dmem_en ; 66 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[0]~25 ; 100 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; sys_clk ; 569 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; sys_res ; 549 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|rtw_rec.imm_set ; 65 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[1]~13 ; 42 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 53 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 81 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[1] ; 103 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_OP~0 ; 32 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; ~GND ; 208 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16 ; 33 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[2]~0 ; 32 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[3]~1 ; 32 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[4]~2 ; 32 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[5]~3 ; 32 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[6]~4 ; 32 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[7]~5 ; 32 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[8]~6 ; 32 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[9]~7 ; 32 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[10]~8 ; 32 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[11]~9 ; 32 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_addr[12]~10 ; 32 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 60 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[1] ; 109 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|WideOr2~0 ; 42 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23 ; 63 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.STACK_OP ; 56 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 50 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[13] ; 34 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.STACK_OP ; 57 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|WideOr2~0 ; 36 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 59 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|Selector74~2 ; 71 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[13] ; 56 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[3]~22 ; 71 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 78 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[2]~16 ; 74 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|data_out~2 ; 80 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM072 ; 71 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|right_operand[2]~16 ; 75 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a1 ; 33 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|calc~2 ; 31 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; 51 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 35 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[31]~0 ; 31 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[31]~2 ; 32 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[3] ; 39 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[2] ; 64 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[31]~0 ; 32 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 40 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 39 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; 32 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|calc~2 ; 31 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 33 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 64 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; 33 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; execute_stage:exec_st|alu:alu_inst|Selector0~0 ; 35 ;
-; Rule T101: Nodes with more than the specified number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 35 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; sys_clk ; 569 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; sys_res ; 549 ;
+; Rule T101: Nodes with more than the specified number of fan-outs ; sys_clk ; 563 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; sys_clk ; 563 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; sys_res ; 543 ;
; Rule T102: Top nodes with the highest number of fan-outs ; ~GND ; 208 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[1] ; 109 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[1] ; 103 ;
; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[0]~25 ; 100 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[1]~19 ; 96 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[1]~19 ; 95 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 81 ;
; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_out~2 ; 80 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 78 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[2]~16 ; 75 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[2]~16 ; 74 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|Selector74~2 ; 71 ;
; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[3]~22 ; 71 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM072 ; 71 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.dmem_en ; 66 ;
; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|rtw_rec.imm_set ; 65 ;
; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 64 ;
; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[2] ; 64 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.dmem_en ; 63 ;
; Rule T102: Top nodes with the highest number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23 ; 63 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 60 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.STACK_OP ; 56 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|left_operand[5]~3 ; 53 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 59 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.STACK_OP ; 57 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[13] ; 56 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|left_operand[5]~3 ; 54 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 53 ;
; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; 51 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 50 ;
; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|right_operand[1]~13 ; 42 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|WideOr2~0 ; 42 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 40 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 39 ;
; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[3] ; 39 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|WideOr2~0 ; 36 ;
; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 35 ;
; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|Selector0~0 ; 35 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|wb_reg.address[13] ; 34 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16 ; 33 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 33 ;
; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; 33 ;
; Rule T102: Top nodes with the highest number of fan-outs ; fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a1 ; 33 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 33 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[31]~2 ; 32 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[2]~0 ; 32 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[3]~1 ; 32 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; 32 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[7]~5 ; 32 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[8]~6 ; 32 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[9]~7 ; 32 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[4]~2 ; 32 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16 ; 33 ;
; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[10]~8 ; 32 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_OP~0 ; 32 ;
; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[11]~9 ; 32 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[3]~1 ; 32 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[9]~7 ; 32 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[7]~5 ; 32 ;
; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[31]~0 ; 32 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[4]~2 ; 32 ;
; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[5]~3 ; 32 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[31]~2 ; 32 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_OP~0 ; 32 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ;
; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[12]~10 ; 32 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[2]~0 ; 32 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; 32 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[6]~4 ; 32 ;
+; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|data_addr[8]~6 ; 32 ;
; Rule T102: Top nodes with the highest number of fan-outs ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[31]~0 ; 31 ;
; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|calc~2 ; 31 ;
-; Rule T102: Top nodes with the highest number of fan-outs ; execute_stage:exec_st|alu:alu_inst|pwr_en~4 ; 30 ;
+------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------+
Info: *******************************************************************
Info: Running Quartus II Design Assistant
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Mon Dec 20 17:38:59 2010
+ Info: Processing started: Mon Dec 20 23:23:37 2010
Info: Command: quartus_drc --read_settings_files=off --write_settings_files=off dt -c dt
-Critical Warning: Synopsys Design Constraints File file not found: 'dt.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info: No user constrained base clocks found in the design
Critical Warning: (High) Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source. Found 12 node(s) related to this rule.
Critical Warning: Node "execute_stage:exec_st|reg.alu_jump"
- Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[0]"
- Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[1]"
Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[2]"
+ Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[1]"
Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[3]"
- Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[4]"
- Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[5]"
+ Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[0]"
Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[6]"
+ Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[5]"
+ Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[4]"
Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[7]"
Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[8]"
Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[9]"
Critical Warning: Node "fetch_stage:fetch_st|instr_r_addr[10]"
Warning: (Medium) Rule R102: External reset signals should be synchronized using two cascaded registers. Found 1 node(s) related to this rule.
Warning: Node "sys_res"
-Info: (Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 49 node(s) with highest fan-out.
+Info: (Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 50 node(s) with highest fan-out.
+ Info: Node "sys_res"
+ Info: Node "fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23"
+ Info: Node "~GND"
+ Info: Node "fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a1"
+ Info: Node "execute_stage:exec_st|left_operand[5]~3"
Info: Node "execute_stage:exec_st|right_operand[1]~19"
Info: Node "writeback_stage:writeback_st|wb_reg.dmem_en"
- Info: Node "execute_stage:exec_st|left_operand[5]~3"
Info: Node "execute_stage:exec_st|right_operand[0]~25"
- Info: Node "sys_clk"
- Info: Node "sys_res"
Info: Node "decode_stage:decode_st|rtw_rec.imm_set"
Info: Node "execute_stage:exec_st|right_operand[1]~13"
+ Info: Node "decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP"
+ Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[3]"
+ Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[1]"
Info: Node "decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_OP~0"
- Info: Node "~GND"
Info: Node "decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16"
Info: Node "writeback_stage:writeback_st|data_addr[2]~0"
Info: Node "writeback_stage:writeback_st|data_addr[3]~1"
Info: Node "writeback_stage:writeback_st|data_addr[4]~2"
Info: Node "writeback_stage:writeback_st|data_addr[5]~3"
+ Info: Node "writeback_stage:writeback_st|data_addr[6]~4"
Info: Node "writeback_stage:writeback_st|data_addr[7]~5"
Info: Node "writeback_stage:writeback_st|data_addr[8]~6"
Info: Node "writeback_stage:writeback_st|data_addr[9]~7"
Info: Node "writeback_stage:writeback_st|data_addr[10]~8"
Info: Node "writeback_stage:writeback_st|data_addr[11]~9"
Info: Node "writeback_stage:writeback_st|data_addr[12]~10"
- Info: Node "decode_stage:decode_st|dec_op_inst.op_group.LDST_OP"
- Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[1]"
- Info: Node "execute_stage:exec_st|alu:alu_inst|WideOr2~0"
- Info: Node "fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23"
Info: Node "decode_stage:decode_st|dec_op_inst.op_group.STACK_OP"
- Info: Node "decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP"
- Info: Node "writeback_stage:writeback_st|wb_reg.address[13]"
- Info: Node "execute_stage:exec_st|right_operand[3]~22"
- Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[3]"
+ Info: Node "execute_stage:exec_st|alu:alu_inst|WideOr2~0"
+ Info: Node "decode_stage:decode_st|dec_op_inst.op_group.LDST_OP"
+ Info: Node "execute_stage:exec_st|alu:alu_inst|Selector74~2"
Info: Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
Info: (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 50 node(s) with highest fan-out.
Info: Node "sys_clk"
Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[1]"
Info: Node "execute_stage:exec_st|right_operand[0]~25"
Info: Node "execute_stage:exec_st|right_operand[1]~19"
- Info: Node "writeback_stage:writeback_st|data_out~2"
Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[3]"
+ Info: Node "writeback_stage:writeback_st|data_out~2"
Info: Node "execute_stage:exec_st|right_operand[2]~16"
+ Info: Node "execute_stage:exec_st|alu:alu_inst|Selector74~2"
Info: Node "execute_stage:exec_st|right_operand[3]~22"
- Info: Node "decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM072"
+ Info: Node "writeback_stage:writeback_st|wb_reg.dmem_en"
Info: Node "decode_stage:decode_st|rtw_rec.imm_set"
Info: Node "decode_stage:decode_st|dec_op_inst.op_group.OR_OP"
Info: Node "writeback_stage:writeback_st|wb_reg.address[2]"
- Info: Node "writeback_stage:writeback_st|wb_reg.dmem_en"
Info: Node "fetch_stage:fetch_st|r_w_ram:instruction_ram|altsyncram:ram_rtl_0|altsyncram_k6k1:auto_generated|ram_block1a23"
Info: Node "decode_stage:decode_st|dec_op_inst.op_group.LDST_OP"
Info: Node "decode_stage:decode_st|dec_op_inst.op_group.STACK_OP"
+ Info: Node "writeback_stage:writeback_st|wb_reg.address[13]"
Info: Node "execute_stage:exec_st|left_operand[5]~3"
- Info: Node "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT"
Info: Node "decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP"
+ Info: Node "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT"
Info: Node "execute_stage:exec_st|right_operand[1]~13"
- Info: Node "execute_stage:exec_st|alu:alu_inst|WideOr2~0"
Info: Node "decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP"
Info: Node "writeback_stage:writeback_st|wb_reg.address[3]"
+ Info: Node "execute_stage:exec_st|alu:alu_inst|WideOr2~0"
Info: Node "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP"
Info: Node "execute_stage:exec_st|alu:alu_inst|Selector0~0"
- Info: Node "writeback_stage:writeback_st|wb_reg.address[13]"
- Info: Node "decode_stage:decode_st|decoder:decoder_inst|instr_spl.op_detail[0]~16"
+ Info: Node "decode_stage:decode_st|dec_op_inst.op_group.AND_OP"
Info: Node "decode_stage:decode_st|dec_op_inst.op_group.XOR_OP"
Info: Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
-Info: Design Assistant information: finished post-fitting analysis of current design -- generated 99 information messages and 13 warning messages
-Info: Quartus II Design Assistant was successful. 0 errors, 16 warnings
- Info: Peak virtual memory: 195 megabytes
- Info: Processing ended: Mon Dec 20 17:39:01 2010
+Info: Design Assistant information: finished post-fitting analysis of current design -- generated 100 information messages and 13 warning messages
+Info: Quartus II Design Assistant was successful. 0 errors, 15 warnings
+ Info: Peak virtual memory: 191 megabytes
+ Info: Processing ended: Mon Dec 20 23:23:39 2010
Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:02
+ Info: Total CPU time (on all processors): 00:00:01
projects / calu.git / blobdiff