copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / writeback_stage_b.vhd

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index acf0f7db2032a88263d11df7b924e9aeac5450a5..f5933678b48accabdc73eae09368b96afca9fc3a 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
@@ -95,6 +116,8 @@ imp : extension_imp
                        new_im_data_out
                );
        
+       rem7seg: if "a" /= "a" generate
+
        altera_7seg: if FPGATYPE /= "s3e" generate
 sseg : extension_7seg
        generic map(
@@ -103,13 +126,15 @@ sseg : extension_7seg
        port map(
                clk,
                reset,
-               ext_7seg,
-               sseg0,
-               sseg1,
-               sseg2,
-               sseg3
+               --ext_7seg,
+               ext_7seg
+               --sseg0,
+               --sseg1,
+               --sseg2,
+               --sseg3
                );
        end generate;
+       end generate;
 
 interrupt : extension_interrupt
        generic map(
@@ -234,7 +259,7 @@ begin
        if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
                jump_addr <= data_ram_read;
        else
-               jump_addr <= result;    
+               jump_addr <= result;
        end if;
 
 --     if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
@@ -269,10 +294,10 @@ begin
        data_addr <= (others => '0');
        dmem_we <= '0';
        
-       if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then
+       if (wb_reg.address(DATA_ADDR_WIDTH+3) /= '1') then
                data_out := data_ram_read;
        else
-               reg_we_v := reg_we_v and ext_anysel;
+               reg_we_v := reg_we_v and (ext_anysel or not(wb_reg.dmem_en));
                data_out := data_ram_read_ext;
        end if;
        
@@ -306,7 +331,7 @@ begin
        
        data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length); 
        
-       if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
+       if (wb_reg_nxt.address(DATA_ADDR_WIDTH+3) /= '1') then
                data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
                dmem_we <= wb_reg_nxt.dmem_write_en;
        end if;