+-- `Deep Thought', a softcore CPU implemented on a FPGA
+--
+-- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+-- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+-- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+-- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+-- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.extension_uart_pkg.all;
use work.extension_7seg_pkg.all;
use work.extension_imp_pkg.all;
+use work.extension_timer_pkg.all;
architecture behav of writeback_stage is
signal calc_mem_res : gp_register_t;
begin
-
- ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
spartan3e: if FPGATYPE = "s3e" generate
new_im_data_out
);
+ rem7seg: if "a" /= "a" generate
+
altera_7seg: if FPGATYPE /= "s3e" generate
sseg : extension_7seg
generic map(
port map(
clk,
reset,
- ext_7seg,
- sseg0,
- sseg1,
- sseg2,
- sseg3
+ --ext_7seg,
+ ext_7seg
+ --sseg0,
+ --sseg1,
+ --sseg2,
+ --sseg3
);
end generate;
+ end generate;
interrupt : extension_interrupt
generic map(
int_req
);
+
+timer : extension_timer
+ generic map(RESET_VALUE)
+ port map(clk, reset, ext_timer, ext_timer_out);
syn: process(clk, reset)
if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
jump_addr <= data_ram_read;
else
- jump_addr <= result;
+ jump_addr <= result;
end if;
-- if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
data_addr <= (others => '0');
dmem_we <= '0';
- if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then
+ if (wb_reg.address(DATA_ADDR_WIDTH+3) /= '1') then
data_out := data_ram_read;
else
- reg_we_v := reg_we_v and ext_anysel;
+ reg_we_v := reg_we_v and (ext_anysel or not(wb_reg.dmem_en));
data_out := data_ram_read_ext;
end if;
data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length);
- if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
+ if (wb_reg_nxt.address(DATA_ADDR_WIDTH+3) /= '1') then
data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
dmem_we <= wb_reg_nxt.dmem_write_en;
end if;
-- when "11" => ext_timer.byte_en <= "1000";
-- when others => null;
-- end case;
- when EXT_GPMP_ADDR =>
- ext_gpmp.sel <= enable;
- ext_anysel <= enable;
+-- when EXT_GPMP_ADDR =>
+ -- ext_gpmp.sel <= enable;
+-- ext_anysel <= enable;
-- ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
-- ext_gpmp.data <= ram_data;
-- ext_gpmp.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);