added byte enable, tested ldi, ldb, stb

[calu.git] / cpu / src / writeback_stage_b.vhd

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 490eb74e15ea0e00c52fbd4318af5037cf611185..a64906b8f96cd936f6f95a03548918ab9926458f 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -29,18 +29,18 @@ begin
        ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
        ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
 
-       data_ram : r_w_ram
+       data_ram : r_w_ram_be
                generic map (
-                       DATA_ADDR_WIDTH,
-                       WORD_WIDTH
+                       DATA_ADDR_WIDTH
                )
                
                port map (
                        clk,
                        data_addr(DATA_ADDR_WIDTH+1 downto 2),
                        data_addr(DATA_ADDR_WIDTH+1 downto 2),
+                       wb_reg_nxt.byte_en,
                        dmem_we,
-                       ram_data,
+                       wb_reg_nxt.data, --ram_data,
                        data_ram_read
                );
 
@@ -118,17 +118,26 @@ begin
                if hword = '1' then
 --                     case address(BYTEADDR-1 downto 0) is
                        case address_val is
-                       when "00" => byte_en(1 downto 0) := "11";
-                       when "10" => byte_en(3 downto 2) := "11";
+                       when "00" => 
+                               byte_en(1 downto 0) := "11";
+                       when "10" => 
+                               byte_en(3 downto 2) := "11";
+                               wb_reg_nxt.data(31 downto 16) <= ram_data(15 downto 0);
                        when others => null;
                        end case;
                elsif byte_s = '1' then
 --                     case address(BYTEADDR-1 downto 0) is
                        case address_val is
                        when "00" => byte_en(0) := '1';
-                       when "01" => byte_en(1) := '1';
-                       when "10" => byte_en(2) := '1';
-                       when "11" => byte_en(3) := '1';
+                       when "01" => 
+                               byte_en(1) := '1';
+                               wb_reg_nxt.data(15 downto 8) <= ram_data(7 downto 0);
+                       when "10" => 
+                               byte_en(2) := '1';
+                               wb_reg_nxt.data(23 downto 16) <= ram_data(7 downto 0);
+                       when "11" => 
+                               byte_en(3) := '1';
+                               wb_reg_nxt.data(31 downto 24) <= ram_data(7 downto 0);
                        when others => null;
                        end case;
                else