pipeline erste version mit 31bit shifter (kostet 7MHz und viele LEs)

[calu.git] / cpu / src / writeback_stage_b.vhd

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 94af88c05e09567d340993b4150934620b50330e..9d8fddeb9d578b08d2a634026d24197f15bcc365 100644 (file)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -38,11 +38,11 @@ syn: process(clk, reset)
 begin
 
        if (reset = RESET_VALUE) then
-               wb_reg_nxt.address <= (others => '0');
-               wb_reg_nxt.dmem_en <= '0';
-               wb_reg_nxt.dmem_write_en <= '0';
-               wb_reg_nxt.hword <= '0';
-               wb_reg_nxt.byte_s <= '0';
+               wb_reg.address <= (others => '0');
+               wb_reg.dmem_en <= '0';
+               wb_reg.dmem_write_en <= '0';
+               wb_reg.hword <= '0';
+               wb_reg.byte_s <= '0';
        elsif rising_edge(clk) then
                wb_reg <= wb_reg_nxt;
        end if;
@@ -58,7 +58,7 @@ end process;
 
 
 
-shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result)
+shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred)
 
 begin
        wb_reg_nxt.address <= address;