ram: reducing instr- and dataram

[calu.git] / cpu / src / writeback_stage_b.vhd

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index fd26a297b8e5727e9f5c2d975c600cb9b35115fd..6a3a4e6c0e11ef5b500e29f9ba24e5ed698d9c40 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -10,6 +10,7 @@ use work.extension_pkg.all;
 use work.extension_uart_pkg.all;
 use work.extension_7seg_pkg.all;
 use work.extension_imp_pkg.all;
+use work.extension_timer_pkg.all;
 
 architecture behav of writeback_stage is
 
@@ -30,8 +31,6 @@ signal sel_nxt, dmem_we, ext_anysel : std_logic;
 signal calc_mem_res : gp_register_t;
 
 begin
-
-       ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
        ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
 
        spartan3e: if FPGATYPE = "s3e" generate
@@ -42,6 +41,7 @@ begin
                port map (
                        clk,
                        data_addr(DATA_ADDR_WIDTH+1 downto 2),
+                       data_addr(DATA_ADDR_WIDTH+1 downto 2),
                        wb_reg_nxt.byte_en,
                        dmem_we,
                        wb_reg_nxt.data, --ram_data,
@@ -68,7 +68,8 @@ begin
 
 uart : extension_uart 
        generic map(
-               RESET_VALUE
+               RESET_VALUE,
+               CLK_BAUD
                )
        port map(
                        clk ,
@@ -125,6 +126,10 @@ interrupt : extension_interrupt
                int_req
 
                );
+
+timer : extension_timer
+       generic map(RESET_VALUE)
+       port map(clk, reset, ext_timer, ext_timer_out);
        
 syn: process(clk, reset)
 
@@ -229,7 +234,7 @@ begin
        if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
                jump_addr <= data_ram_read;
        else
-               jump_addr <= result;    
+               jump_addr <= result;
        end if;
 
 --     if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
@@ -264,7 +269,7 @@ begin
        data_addr <= (others => '0');
        dmem_we <= '0';
        
-       if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then
+       if (wb_reg.address(DATA_ADDR_WIDTH+3) /= '1') then
                data_out := data_ram_read;
        else
                reg_we_v := reg_we_v and ext_anysel;
@@ -301,7 +306,7 @@ begin
        
        data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length); 
        
-       if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
+       if (wb_reg_nxt.address(DATA_ADDR_WIDTH+3) /= '1') then
                data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
                dmem_we <= wb_reg_nxt.dmem_write_en;
        end if;
@@ -448,9 +453,9 @@ begin
                                -- when "11" => ext_timer.byte_en <= "1000";
                                -- when others => null;
                        -- end case;
-       when EXT_GPMP_ADDR => 
-               ext_gpmp.sel <= enable;
-               ext_anysel <= enable;
+--     when EXT_GPMP_ADDR => 
+ --            ext_gpmp.sel <= enable;
+--             ext_anysel <= enable;
                -- ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
                -- ext_gpmp.data <= ram_data;
                -- ext_gpmp.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);