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[calu.git] / cpu / src / writeback_stage_b.vhd

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index a1b08b8f09dbf18a97eda8b4e958fed5e356ca3a..585e0e2002a3669e684b848e88490ece053802ab 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -192,7 +192,7 @@ end process;
 
 
 
-out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel)
+out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel, result)
 variable reg_we_v : std_logic;
 variable data_out : gp_register_t;
 begin
@@ -222,7 +222,7 @@ begin
                data_out(4*byte_t'length-1 downto 3*byte_t'length) := (others => '0');
        end if;
        
-       data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))); 
+       data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length); 
        
        if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
                data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
@@ -231,6 +231,10 @@ begin
        
        regfile_val <= data_out;
        
+       if wb_reg.dmem_en = '0' then
+               regfile_val <= result;
+       end if;
+       
        reg_we <= reg_we_v;
        
 end process;