instruction memory progammer: is in and works in simulations

[calu.git] / cpu / src / writeback_stage.vhd

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index d4d669c5d936f708e2ddf00b0c9fbb08800720d5..aacba01de09a655846e40b1ba7b08d0b92ffbf10 100644 (file)
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -38,6 +38,10 @@ entity writeback_stage is
                        -- hallo stefan mir adden da jetzt mal schnell an uart port :D
                        bus_tx : out std_logic;
                        bus_rx : in std_logic;
+                       -- instruction memory program port :D
+                       new_im_data_out : out std_logic;
+                       im_addr : out gp_register_t;
+                       im_data : out gp_register_t;
                        
                        sseg0 : out std_logic_vector(0 to 6);
                        sseg1 : out std_logic_vector(0 to 6);