instr mem durch case, fibonacci als programm, 7seg als extension geadded, resultat...

[calu.git] / cpu / src / writeback_stage.vhd

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index 4c1364c3e597bacccd3e3d945ea2d9442dd9f43c..73c5df43499e1401bc04a496f9cc5b941d0cab4a 100644 (file)
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -36,7 +36,12 @@ entity writeback_stage is
                        jump_addr : out instruction_addr_t;
                        jump : out std_logic;
                        -- hallo stefan mir adden da jetzt mal schnell an uart port :D
-                       bus_tx : out std_logic
+                       bus_tx : out std_logic;
+                       
+                       sseg0 : out std_logic_vector(0 to 6);
+                       sseg1 : out std_logic_vector(0 to 6);
+                       sseg2 : out std_logic_vector(0 to 6);
+                       sseg3 : out std_logic_vector(0 to 6)
                );
                
 end writeback_stage;