+-- `Deep Thought', a softcore CPU implemented on a FPGA
+--
+-- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+-- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+-- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+-- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+-- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
+use work.common_pkg.all;
+
entity writeback_stage is
generic (
RESET_VALUE : std_logic;
-- active logic value
LOGIC_ACT : std_logic;
-
+ FPGATYPE : string;
+ CLK_BAUD : integer
);
port(
--System inputs
ram_data : in word_t; --ureg
alu_jmp : in std_logic; --reg
br_pred : in std_logic; --reg
- write_en : in std_logic; --reg (register file)
+ write_en : in std_logic; --reg (register file) bei jump 1 wenn addr in result
dmem_en : in std_logic; --ureg (jump addr in mem or in address)
dmem_write_en : in std_logic; --ureg
hword : in std_logic; --ureg
reg_we : out std_logic;
reg_addr : out gp_addr_t;
jump_addr : out instruction_addr_t;
- jump : out std_logic
+ jump : out std_logic;
+ -- hallo stefan mir adden da jetzt mal schnell an uart port :D
+ bus_tx : out std_logic;
+ bus_rx : in std_logic;
+ -- instruction memory program port :D
+ new_im_data_out : out std_logic;
+ im_addr : out gp_register_t;
+ im_data : out gp_register_t;
+
+ --sseg0 : out std_logic_vector(0 to 6);
+ --sseg1 : out std_logic_vector(0 to 6);
+ --sseg2 : out std_logic_vector(0 to 6);
+ --sseg3 : out std_logic_vector(0 to 6);
+
+ int_req : out interrupt_t
+
);
end writeback_stage;