architecture behaviour of rom is
- subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
- type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
-
- -- r0 = 0, r1 = 1, r2 = 3, r3 = A
-
- signal rrrr_addr : std_logic_vector(31 downto 0);
+ signal vsim_bug : std_logic_vector(31 downto 0);
begin
process(clk)
-- data_out <= ram(to_integer(UNSIGNED(rd_addr)));
- case rrrr_addr(10 downto 0) is
-
+ --case rrrr_addr(10 downto 0) is
+ case vsim_bug(6 downto 0) is
-- fibonacci
-- when "00000000000" => data_out <= "11101101000000000000000000000000"; --
-- when "00000000001" => data_out <= "11101101001000000000000000000000"; --
--
-- when "00000011101" => data_out <= x"ed510058";
-- when "00000011110" => data_out <= x"e7850000";
---
+
-- uart echo
+
+--1;00000000;ed010058;ldi r0, 0x200B;;
+--1;00000004;ed090060;ldi r1, 0x200C;;
+--1;00000008;ed110080;ldi r2, 0x2010;;
+--1;0000000c;e7188000;ldw r3, 0(r1);;
+--1;00000010;ec1a0000;cmp r3, r4;;
+--1;00000014;1b7ffd81;breq 0;;
+--1;00000018;e7980000;stw r3, 0(r0);;
+--1;0000001c;e7990000;stw r3, 0(r2);;
+--1;00000020;e1218000;addi r4, r3, 0;;
+--1;00000024;eb7ffb81;br 0;;
- when "00000000000" => data_out <= x"ed010058";
- when "00000000001" => data_out <= x"ed090060";
- when "00000000010" => data_out <= x"e5860000"; --x"e7188000";
- when "00000000011" => data_out <= x"e5a00000"; --x"ec1a0000";
- when "00000000100" => data_out <= x"1b7ffe01";
- when "00000000101" => data_out <= x"e7980000";
- when "00000000110" => data_out <= x"e1218000";
- when "00000000111" => data_out <= x"eb7ffc81";
+-- when "0000000" => data_out <= x"ed010058";
+-- when "0000001" => data_out <= x"ed090060";
+-- when "0000010" => data_out <= x"ed110080"; --x"e7188000"; f
+-- when "0000011" => data_out <= x"e7188000"; --x"ec1a0000";
+-- when "0000100" => data_out <= x"ec1a0000";
+-- when "0000101" => data_out <= x"1b7ffe01";
+-- when "0000110" => data_out <= x"e7990000"; -- f
+-- when "0000111" => data_out <= x"e7980000";
+-- when "0001000" => data_out <= x"e1218000";
+-- when "0001001" => data_out <= x"eb7ffb81";
+
+--1;00000000;ed010058;ldi r0, 0x200B;;;
+--1;00000004;ed090060;ldi r1, 0x200C;;;
+--1;00000008;ed110080;ldi r2, 0x2010;;;
+--1;0000000c;ed390078;ldi r7, 0x200F;;;
+--1;00000010;ed480012;ldih r9, 0x0002;;;
+--1;00000014;e7438000;ldw r8, 0(r7);;;
+--1;00000018;e254c000;and r10, r9, r8;;;
+--1;0000001c;07188000;ldwnz r3, 0(r1);;;
+--1;00000020;07980000;stwnz r3, 0(r0);;;
+--1;00000024;07990000;stwnz r3, 0(r2);;;
+--1;00000028;eb7ffb01;br 0;;;
-
- when others => data_out <= "11101011000000000000000000000010";
+--uart test:
+-- when "0000000" => data_out <= x"ed010058";
+-- when "0000001" => data_out <= x"ed090060";
+-- when "0000010" => data_out <= x"ed110080"; --x"e7188000"; f
+-- when "0000011" => data_out <= x"ed390000"; --x"ec1a0000";
+-- when "0000100" => data_out <= x"ed480012";
+-- when "0000101" => data_out <= x"e7438000";
+-- when "0000110" => data_out <= x"e254c000"; -- f
+-- when "0000111" => data_out <= x"07188000";
+-- when "0001000" => data_out <= x"07980000";
+-- when "0001001" => data_out <= x"07990000";
+-- when "0001010" => data_out <= x"eb7ffb81";
+
+-------------------------------------------
+
+-- when "00000000000" => data_out <= x"ed000000";
+-- when "00000000001" => data_out <= x"ed080008";
+-- when "00000000010" => data_out <= x"e9880000"; --x"e7188000"; f
+-- when "00000000011" => data_out <= x"e5088400"; --x"ec1a0000";
+-- when "00000000100" => data_out <= x"e9880001";
+-- when "00000000101" => data_out <= x"e7180000";
+-- when "00000000110" => data_out <= x"e9200001"; -- f
+-- when "00000000111" => data_out <= x"e7a00004";
+-- when "00000001000" => data_out <= x"e7280004";
+-- -- when "00000001001" => data_out <= x"eb7ffb81";
+ when "0000000" => data_out <= x"eb000183"; -- br+ main
+ when "0000001" => data_out <= x"eb000103"; -- br+ main
+ when "0000010" => data_out <= x"eb000008"; -- ret
+ when "0000011" => data_out <= x"ed010000"; -- ldi r0, 0x2000
+ when "0000100" => data_out <= x"ed090058"; -- ldi r1, 0x200b
+ when "0000101" => data_out <= x"ed110060"; -- ldi r2, 0x200c
+ when "0000110" => data_out <= x"e7280000"; -- ldw r5, 0(r0)
+ when "0000111" => data_out <= x"e2a80010"; -- andx r5, 0x2
+ when "0001000" => data_out <= x"1b7ffd83"; -- brzs+ main
+ when "0001001" => data_out <= x"e7390000"; -- ldw r7, 0(r2)
+ when "0001010" => data_out <= x"e7280000"; -- ldw r5, 0(r0)
+ when "0001011" => data_out <= x"e2a80008"; -- andx r5, 0x1
+ when "0001100" => data_out <= x"0b7fff03"; -- brnz+ uartnrdy
+ when "0001101" => data_out <= x"e7b88000"; -- stw r7, 0(r1)
+ when "0001110" => data_out <= x"eb7ffa81"; -- br main
+ -- just nop until rom end!
+ when others => data_out <= x"fd000000";
end case;
-
- if wr_en = '1' then
- end if;
end if;
end process;
- rrrr_addr(10 downto 0) <= rd_addr;
- rrrr_addr(31 downto 11) <= (others => '0');
+ vsim_bug(6 downto 0) <= rd_addr;
+ vsim_bug(31 downto 7) <= (others => '0');
end architecture behaviour;
projects / calu.git / blobdiff