copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / r_w_ram_b.vhd

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
old mode 100755 (executable)
new mode 100644 (file)
index 50c7660..f795dc1
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -1,24 +1,50 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library ieee;
 
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
+use work.mem_pkg.all;
+
 architecture behaviour of r_w_ram is
 
        subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
-       signal ram : RAM_TYPE; --:= (others=> x"00");
-
+       signal ram : RAM_TYPE := (others => x"00000000");
+       
 begin
        process(clk)
        begin
                if rising_edge(clk) then
-                       data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+                data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+
+
                        
                        if wr_en = '1' then
                                ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
                        end if;
                end if;
        end process;
+       
 end architecture behaviour;