copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / r_w_ram_b.vhd

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 1c8b21209708acf65e31297b7a2629941c5ad074..f795dc1ca76aa2be70245618bd11098931ac2c56 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library ieee;
 
 use IEEE.std_logic_1164.all;
@@ -10,38 +31,20 @@ architecture behaviour of r_w_ram is
        subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
-       signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0
-                                   1 => "11100000000110001000000000000000", --add r3, r1, r0
-                                   2 => "11100000001000011001000000000000", --add r4, r3, r2
-                                   3 => "11100000000100001000000000000000", --add r2, r1, r0
-                                   4 => "11100000000110001000000000000000", --add r3, r1, r0
-                                   5 => "11100000001000011001000000000000", --add r4, r3, r2
-                                   6 => "11101100000000001000000000000000", --cmp r0 , r1 
-                                   7 => "00000000001010101010000000000001", --addnqd r5, r5, r4
-                                   8 => "00000000001010101010000000000000", --addnq r5, r5, r4
-                                   9 => "11101100001000100000000000000000", --cmp r4 , r4 
-                                  10 => "00000001001100001000000001010000", --addinq r5, r1, 10
-                                  11 => "00010001001100001000000001010000", --addieq r5, r1, 10 
-                                  12 => "00010001101100110000000001010000", --subieq r5, r5, 10
-                                  13 => "11100000000100001000000000000000", --add r2, r1, r0
-                                  14 => "11100010000100001000000000000000", --and r2, r1, r0
-                                  15 => "11101100000000001000000000000000", --cmp r0 , r1 
-                                  16 => "10000000001010101010000000000001", --addabd r5, r5, r4
-                                  17 => "10110011101110001000010000110001", --orxltd r7, 1086
-                                  18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1
-                                  19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2
-                                 others => x"F0000000");
-
-
+       signal ram : RAM_TYPE := (others => x"00000000");
+       
 begin
        process(clk)
        begin
                if rising_edge(clk) then
-                       data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+                data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+
+
                        
                        if wr_en = '1' then
                                ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
                        end if;
                end if;
        end process;
+       
 end architecture behaviour;