pipe v1

[calu.git] / cpu / src / r_w_ram_b.vhd

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index f03388593c6ec05dddd76dd1604e820f0a3641f7..c9de81aab4d9d41194836885abee7ac44d67ccdb 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -11,7 +11,7 @@ architecture behaviour of r_w_ram is
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
        signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000", 
-                                 1 => "11100000000000001001000000000000", 
+                                 1 => "11110000000000001001000000000000", 
                                  2 => "11100000000010001001000000000000", 
                                  3 => "11100001000110010111011001101100", 
                                  others => x"00000000");