fetch und decode kompilierbar, generelle tb, änderung in pkgs, eigene decoder entity

[calu.git] / cpu / src / r2_w_ram_b.vhd

diff --git a/cpu/src/r2_w_ram_b.vhd b/cpu/src/r2_w_ram_b.vhd
index 4350511f196797983222d64f533ec221602a2c08..84a3a94b150f6747a4319645f7c37f86e01810c3 100644 (file)
--- a/cpu/src/r2_w_ram_b.vhd
+++ b/cpu/src/r2_w_ram_b.vhd
@@ -3,12 +3,14 @@ library ieee;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
+use work.mem_pkg.all;
+
 architecture behaviour of r2_w_ram is
 
        subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
-       signal ram : RAM_TYPE; --:= (others=> x"00");
+       signal ram : RAM_TYPE := (others=> x"00000001");
 
 begin
        process(clk)