copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / r2_w_ram_b.vhd

diff --git a/cpu/src/r2_w_ram_b.vhd b/cpu/src/r2_w_ram_b.vhd
index d067ad3a9589ec053ac9a67edb6e52bec2da58fe..2ea1409fdbdeda2b1d7de10682e3b1a4272b24f6 100644 (file)
--- a/cpu/src/r2_w_ram_b.vhd
+++ b/cpu/src/r2_w_ram_b.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library ieee;
 
 use IEEE.std_logic_1164.all;
@@ -12,10 +33,10 @@ architecture behaviour of r2_w_ram is
        
        signal ram : RAM_TYPE := (
                                0 => x"00000000",
-                               1 => x"00000001",
-                               2 => x"00000002",
-                               3 => x"00000003",
-                               others=> x"00000000");
+                               1 => x"00000000",
+                               2 => x"00000000",
+                               3 => x"00000000",
+                               others=> (others => '0'));
 
 begin
        process(clk)