instr mem durch case, fibonacci als programm, 7seg als extension geadded, resultat...

[calu.git] / cpu / src / pipeline_tb.vhd

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index d87cee18d26c4f271b2cc9e479f89c26840b2d72..8539c425f568c71fc42d6381affabb26a14fd5e9 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -48,7 +48,7 @@ architecture behavior of pipeline_tb is
                  signal dmem_pin  : std_logic;--memop
                  signal dmem_wr_en_pin : std_logic;
                  signal hword_pin  : std_logic;
-                 signal byte_s_pin : std_logic;
+                 signal byte_s_pin, tx_pin : std_logic;
                                 
                                  signal gpm_in_pin : extmod_rec;
                                 signal gpm_out_pin : gp_register_t;
@@ -56,6 +56,8 @@ architecture behavior of pipeline_tb is
 
                 signal cycle_cnt : integer;
 
+               signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
+
 
 begin
 
@@ -133,7 +135,7 @@ begin
                 generic map('0', '1')
                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, sseg0, sseg1, sseg2, sseg3);