signal branch_prediction_bit_pin : std_logic;
signal alu_jump_bit_pin : std_logic;
signal instruction_pin : instruction_word_t;
+ signal prog_cnt : instruction_addr_t;
signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
signal reg_wr_data_pin : gp_register_t;
alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
--Data outputs
- instruction => instruction_pin --: out instruction_word_t
- );
+ instruction => instruction_pin, --: out instruction_word_t
+ prog_cnt => prog_cnt
+ );
decode_st : decode_stage
generic map (
--Data inputs
instruction => instruction_pin, --: in instruction_word_t;
+ prog_cnt => prog_cnt,
reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
reg_we => reg_we_pin, --: in std_logic;