instruction memory progammer: is in and works in simulations

[calu.git] / cpu / src / pipeline_tb.vhd

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index de276a8fc8f305a9cdb46437ca626d3b1a484eb1..0bdcaca896d5b82b17fbbe6bd911ecbdec7fe861 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -61,6 +61,9 @@ architecture behavior of pipeline_tb is
                signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
                signal int_req_pin : interrupt_t;
 
+               signal new_im_data :std_logic;
+               signal im_addr, im_data : gp_register_t;
+
 begin
 
 --             instruction_ram : r_w_ram
@@ -95,6 +98,9 @@ begin
                        prediction_result => prediction_result_pin, --: in instruction_addr_t;
                        branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
                        alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
+                       new_im_data_in => new_im_data,
+                       im_addr => im_addr,
+                       im_data => im_data,
 
                --Data outputs
                        instruction => instruction_pin, --: out instruction_word_t
@@ -138,7 +144,7 @@ begin
                 generic map('0', '1')
                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, sseg0, sseg1, sseg2, sseg3, int_req_pin);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin);