copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / mem_pkg.vhd

diff --git a/cpu/src/mem_pkg.vhd b/cpu/src/mem_pkg.vhd
old mode 100755 (executable)
new mode 100644 (file)
index cba7fd6..87533c4
--- a/cpu/src/mem_pkg.vhd
+++ b/cpu/src/mem_pkg.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 
 use IEEE.std_logic_1164.all;
@@ -23,8 +44,46 @@ package mem_pkg is
                        data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
                );
        end component r_w_ram;
-       
-       component r2_w_ram is
+
+       component r_w_ram_be is
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               clk : in std_logic;
+
+               waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+               be : in std_logic_vector (3 downto 0);
+               
+               we : in std_logic;
+
+               wdata : in std_logic_vector(31 downto 0);
+               
+               q : out std_logic_vector(31 downto 0)
+       );
+       end component r_w_ram_be;
+
+       component ram_xilinx is
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               clk : in std_logic;
+
+               waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+               be : in std_logic_vector (3 downto 0);
+               
+               we : in std_logic;
+
+               wdata : in std_logic_vector(31 downto 0);
+               
+               q : out std_logic_vector(31 downto 0)
+       );
+       end component ram_xilinx;
+
+       component rom is
        generic (
                                ADDR_WIDTH : integer range 1 to integer'high;
                                DATA_WIDTH : integer range 1 to integer'high
@@ -33,17 +92,13 @@ package mem_pkg is
                --System inputs
                        clk : in std_logic;
                --Input
-                       wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-                       
-                       wr_en : in std_logic;
-                       data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
-                       
+                       rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);                   
                --Output
-                       data_out1, data_out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
+                       data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
                );
-       end component r2_w_ram;
+       end component rom;
        
-       component rw2_ram is
+       component r2_w_ram is
        generic (
                                ADDR_WIDTH : integer range 1 to integer'high;
                                DATA_WIDTH : integer range 1 to integer'high
@@ -58,11 +113,11 @@ package mem_pkg is
                        data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
                        
                --Output
-                       out1, out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
+                       data_out1, data_out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
                );
-       end component rw2_ram;
+       end component r2_w_ram;
        
-       component rw_ram is
+       component rw_r_ram is
        generic (
                                ADDR_WIDTH : integer range 1 to integer'high;
                                DATA_WIDTH : integer range 1 to integer'high
@@ -71,14 +126,14 @@ package mem_pkg is
                --System inputs
                        clk : in std_logic;
                --Input
-                       wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+                       rw_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
                        
                        wr_en : in std_logic;
                        data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
                        
                --Output
-                       out1, out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
+                       rw_out, rd_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
                );
-       end component rw_ram;
+       end component rw_r_ram;
 
 end package mem_pkg;