+-- `Deep Thought', a softcore CPU implemented on a FPGA
+--
+-- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+-- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+-- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+-- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+-- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
signal instr_r_addr_nxt : instruction_addr_t;
signal instr_we : std_logic;
signal instr_wr_data : instruction_word_t;
-signal instr_rd_data : instruction_word_t;
+signal instr_rd_data_rom, instr_rd_data : instruction_word_t;
+signal rom_ram, rom_ram_nxt : std_logic;
begin
port map (
clk,
- instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
+ im_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
- instr_we,
- instr_wr_data,
+ new_im_data_in,
+ im_data,
instr_rd_data
);
+
+ instruction_rom : rom
+ generic map (
+ ROM_INSTR_ADDR_WIDTH,
+ WORD_WIDTH
+ )
+
+ port map (
+ clk,
+ instr_r_addr_nxt(ROM_INSTR_ADDR_WIDTH-1 downto 0),
+ instr_rd_data_rom
+ );
+
syn: process(clk, reset)
if (reset = RESET_VALUE) then
instr_r_addr <= (others => '0');
+ rom_ram <= ROM_USE;
+ led2 <= '0';
elsif rising_edge(clk) then
instr_r_addr <= instr_r_addr_nxt;
+ rom_ram <= rom_ram_nxt;
+ led2 <= rom_ram; --rom_ram_nxt;
end if;
end process;
-asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data)
-
+asyn: process(reset, s_reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
+variable instr_pc : instruction_addr_t;
begin
-
- instruction <= instr_rd_data;
- instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
+ rom_ram_nxt <= rom_ram;
+
+ case rom_ram is
+ when ROM_USE =>
+ instruction <= instr_rd_data_rom;
+ when RAM_USE =>
+ instruction <= instr_rd_data;
+ when others =>
+ instruction <= x"F0000000";
+ end case;
+ instr_pc := std_logic_vector(unsigned(instr_r_addr) + 1);
+ instr_r_addr_nxt <= instr_pc;
+
+ if (instr_pc = x"0000007f" and rom_ram = ROM_USE) then
+ rom_ram_nxt <= RAM_USE;
+ instr_r_addr_nxt <= (others => '0');
+ end if;
if (reset = RESET_VALUE) then
instr_r_addr_nxt <= (others => '0');
end if;
- if (alu_jump_bit = LOGIC_ACT) then
+ if (alu_jump_bit = LOGIC_ACT and int_req = IDLE) then
instr_r_addr_nxt <= jump_result;
instruction(31 downto 28) <= "1111";
elsif (branch_prediction_bit = LOGIC_ACT) then
instr_r_addr_nxt <= prediction_result;
end if;
+ case int_req is
+ when UART =>
+ instruction(31 downto 0) <= (others => '0');
+ instruction(31 downto 28) <= "1110";
+ instruction(27 downto 23) <= "10110";
+ instruction(PHYS_INSTR_ADDR_WIDTH + 7 - 1 downto 7) <= UART_INT_VECTOR;
+ instruction(6 downto 4) <= "001";
+ instruction(3 downto 2) <= "01";
+ instruction(1 downto 0) <= "10";
+
+-- instr_r_addr_nxt <= instr_r_addr;
+ when others => null;
+ end case;
+
+ if (s_reset = RESET_VALUE) then
+ rom_ram_nxt <= RAM_USE;
+ instr_r_addr_nxt <= (others => '0');
+ end if;
+
end process;
-prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
-prog_cnt(31 downto 11) <= (others => '0');
+out_logic : process (instr_r_addr, alu_jump_bit, int_req, jump_result)
+
+begin
+ prog_cnt(PHYS_INSTR_ADDR_WIDTH-1 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
+ prog_cnt(INSTR_ADDR_WIDTH-1 downto PHYS_INSTR_ADDR_WIDTH) <= (others => '0');
+
+ if (int_req /= IDLE and alu_jump_bit = LOGIC_ACT ) then
+ prog_cnt(PHYS_INSTR_ADDR_WIDTH-1 downto 0) <= jump_result(PHYS_INSTR_ADDR_WIDTH-1 downto 0);
+ end if;
+
+end process;
end behav;
projects / calu.git / blobdiff