copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / fetch_stage.vhd

diff --git a/cpu/src/fetch_stage.vhd b/cpu/src/fetch_stage.vhd
index c81e2ac14affda3e8addf55cbd590b220cf3a1d4..cf5e7f4c49968fd9bd93ebd94109478a1737d4c8 100644 (file)
--- a/cpu/src/fetch_stage.vhd
+++ b/cpu/src/fetch_stage.vhd
@@ -1,8 +1,30 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
-use work.common_pkg;
+use work.common_pkg.all;
+use work.core_pkg.all;
 
 entity fetch_stage is
 
@@ -10,22 +32,31 @@ entity fetch_stage is
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic;
+                       LOGIC_ACT : std_logic
                        
                        );
        port(
                --System inputs
                        clk : in std_logic;
                        reset : in std_logic;
+                       s_reset : in std_logic;
                
                --Data inputs
                        jump_result : in instruction_addr_t;
                        prediction_result : in instruction_addr_t;
                        branch_prediction_bit : in std_logic;
                        alu_jump_bit : in std_logic;
+                       int_req : in interrupt_t;
+               -- instruction memory program port :D
+                       new_im_data_in : in std_logic;
+                       im_addr : in gp_register_t;
+                       im_data : in gp_register_t;
 
                --Data outputs
-                       instruction : out instruction_word_t
+                       instruction : out instruction_word_t;
+                       prog_cnt : out instruction_addr_t;
+               -- debug
+                       led2 : out std_logic
                );
                
 end fetch_stage;