uart: sollte jetzt eigentlich alles gehen

[calu.git] / cpu / src / extension_uart_pkg.vhd

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
index 80df4b27627ac3298b7589e30114246cddd14c4b..60f2ffa00c6626b9c32284acc367056b11e8f7fd 100644 (file)
--- a/cpu/src/extension_uart_pkg.vhd
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -19,10 +19,10 @@ subtype uart_data is std_logic_vector(UART_WIDTH-1 downto 0);
 constant BAUD_RATE_WITH : integer := 16;
 subtype baud_rate_l is std_logic_vector(BAUD_RATE_WITH-1 downto 0);
 --CLKs
-constant CLK_FREQ_MHZ : real := 33.33;
-constant BAUD_RATE : integer := 115200;
+--constant CLK_FREQ_MHZ : real := 33.33;
+--constant BAUD_RATE : integer := 115200;
 --constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
-constant CLK_PER_BAUD : integer := 16330000;
+constant CLK_PER_BAUD : integer := 434;
 
  component extension_uart is
         --some modules won't need all inputs/outputs
@@ -83,7 +83,8 @@ component rs232_rx is
 
                --To sendlogic
                new_rx_data : out std_logic;
-               rx_data : out uart_data
+               rx_data : out uart_data;
+               bd_rate : in baud_rate_l
        );
 end component rs232_rx;