+-- `Deep Thought', a softcore CPU implemented on a FPGA
+--
+-- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+-- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+-- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+-- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+-- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture behav of extension_uart is
signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
-signal new_wb_data, new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
+signal new_bus_rx,new_wb_data, new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
signal bd_rate : baud_rate_l;
+signal rx_data : std_logic_vector(7 downto 0);
+
+signal uart_int_nxt : std_logic;
+signal uart_data_read_nxt : std_logic;
begin
w3_uart_send(byte_t'range),
tx_rdy,
bd_rate,
- w1_st_co(0)
+ w1_st_co(16)
);
+rs232_rx_inst : rs232_rx
+generic map(
+ RESET_VALUE,
+ 2
+ )
+port map(
+ --System inputs
+ clk,
+ reset,
+
+ --Bus
+ bus_rx,
+
+ --From/to sendlogic
+ new_bus_rx,
+ rx_data,
+ bd_rate
+);
syn : process (clk, reset)
begin
- if (reset = RESET_VALUE) then
- w1_st_co <= (others=>'0');
- w2_uart_config <= (others=>'0');
- w3_uart_send <= (others=>'0');
- w4_uart_receive <= (others=>'0');
-
-
- elsif rising_edge(clk) then
- w1_st_co <= w1_st_co_nxt;
- w2_uart_config <= w2_uart_config_nxt;
- w3_uart_send <= w3_uart_send_nxt;
- w4_uart_receive <= w4_uart_receive_nxt;
- new_tx_data <= new_tx_data_nxt;
- tx_rdy_int <= tx_rdy;
- end if;
+ if (reset = RESET_VALUE) then
+ w1_st_co <= (others=>'0');
+ w2_uart_config(31 downto 16) <= (others=>'0');
+ w2_uart_config(15 downto 0) <= std_logic_vector(to_unsigned(CLK_PER_BAUD, 16));
+ w3_uart_send <= (others=>'0');
+ w4_uart_receive <= (others=>'0');
+ tx_rdy_int <= '0';
+ new_tx_data <= '0';
+ uart_int <= '0';
+
+ elsif rising_edge(clk) then
+ w1_st_co <= w1_st_co_nxt;
+ w2_uart_config <= w2_uart_config_nxt;
+ w3_uart_send <= w3_uart_send_nxt;
+ w4_uart_receive <= w4_uart_receive_nxt;
+ new_tx_data <= new_tx_data_nxt;
+ tx_rdy_int <= tx_rdy;
+ uart_int <= uart_int_nxt;
+ end if;
end process syn;
-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
-gwriten : process (ext_reg,tx_rdy)
+gwriten : process
+ (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read_nxt)
variable tmp_data : gp_register_t;
begin
+ uart_int_nxt <= '0';
+ w1_st_co_nxt <= w1_st_co;
+ w2_uart_config_nxt <= w2_uart_config;
+ w3_uart_send_nxt <= w3_uart_send;
+ w4_uart_receive_nxt <= w4_uart_receive;
+
if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
tmp_data := (others =>'0');
if ext_reg.byte_en(0) = '1' then
when "01" =>
w2_uart_config_nxt <= tmp_data;
when "10" =>
- w1_st_co_nxt(16) <= '1'; -- busy flag set
+ w1_st_co_nxt(0) <= '1'; -- busy flag set
w3_uart_send_nxt <= tmp_data;
when "11" =>
- w4_uart_receive_nxt <= tmp_data;
+ --w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
when others => null;
end case;
- else
- w1_st_co_nxt <= w1_st_co;
- w2_uart_config_nxt <= w2_uart_config;
- w3_uart_send_nxt <= w3_uart_send;
- w4_uart_receive_nxt <= w4_uart_receive;
end if;
if tx_rdy = '1' and tx_rdy_int = '0' then
- w1_st_co_nxt(16) <= '0'; -- busy flag reset
+ w1_st_co_nxt(0) <= '0'; -- busy flag reset
end if;
+ if new_bus_rx = '1' then
+ w4_uart_receive_nxt(7 downto 0) <= rx_data;
+ w1_st_co_nxt(1) <= '1';
+ uart_int_nxt <= '1';
+ end if;
+
+ if (uart_data_read_nxt = '1' and w1_st_co(1) = '1' and ext_reg.sel = '1') then
+ w1_st_co_nxt(1) <= '0';
+ end if;
+
end process gwriten;
-gread : process (clk,ext_reg)
+gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
variable tmp_data : gp_register_t;
begin
+
+ uart_data_read_nxt <= '0';
+
if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
case ext_reg.addr(1 downto 0) is
when "00" =>
end if;
data_out <= tmp_data;
when "11" =>
- tmp_data := (others =>'0');
+ tmp_data := (others =>'0');
+ uart_data_read_nxt <= '1';
if ext_reg.byte_en(0) = '1' then
tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
end if;
-------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
-dataprocess : process (ext_reg,tx_rdy)
+dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
begin