copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / extension_uart_b.vhd

diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd
index 09cec401b335ea2bcb8f1767de17d7faee7d5857..c0462cce4165ab209c309f43bbbfbd1167fd6ad1 100644 (file)
--- a/cpu/src/extension_uart_b.vhd
+++ b/cpu/src/extension_uart_b.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
@@ -69,7 +90,7 @@ begin
    if (reset = RESET_VALUE) then
                        w1_st_co <= (others=>'0');
                        w2_uart_config(31 downto 16) <= (others=>'0');
-                       w2_uart_config(15 downto 0) <= std_logic_vector(to_unsigned(CLK_PER_BAUD, 16)); -- x"0822"; -- x"01B2";
+                       w2_uart_config(15 downto 0) <= std_logic_vector(to_unsigned(CLK_PER_BAUD, 16));
                        w3_uart_send <= (others=>'0');
                        w4_uart_receive <= (others=>'0');
                        tx_rdy_int <= '0';