uart: sollte jetzt eigentlich alles gehen

[calu.git] / cpu / src / extension_uart_b.vhd

diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd
index 5dd8774d76565c34f97fa37b6a957f79164e261e..9f64cf5e0f2210e3d89a4631926b7d50a0239165 100644 (file)
--- a/cpu/src/extension_uart_b.vhd
+++ b/cpu/src/extension_uart_b.vhd
@@ -52,7 +52,8 @@ port map(
 
        --From/to sendlogic
        new_bus_rx,
-       rx_data
+       rx_data,
+       bd_rate
 );
 
 
@@ -62,7 +63,9 @@ syn : process (clk, reset)
 begin
         if (reset = RESET_VALUE) then
                w1_st_co <= (others=>'0');
-               w2_uart_config <= (others=>'0');
+               w2_uart_config(31 downto 16) <= (others=>'0');
+               -- todo mit einer konstante versehen
+               w2_uart_config(15 downto 0) <= x"01B2";
                w3_uart_send <= (others=>'0');
                w4_uart_receive <= (others=>'0');
                tx_rdy_int <= '0';
@@ -115,7 +118,7 @@ begin
                        w1_st_co_nxt(16) <= '1'; -- busy flag set
                        w3_uart_send_nxt <= tmp_data;
                when "11" =>
-                       w4_uart_receive_nxt <= tmp_data;
+                       --w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
                when others => null;
                end case;
        end if;
@@ -124,6 +127,12 @@ begin
                w1_st_co_nxt(16) <= '0'; -- busy flag reset     
        end if;
 
+       if new_bus_rx = '1' then
+               w4_uart_receive_nxt(7 downto 0) <= rx_data;
+               w1_st_co_nxt(17) <= '1';
+       end if;
+       
+
 end process gwriten;
 
 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)