signal rx_data : std_logic_vector(7 downto 0);
signal uart_int_nxt : std_logic;
-
-signal uart_data_read, uart_data_read_nxt : std_logic;
+signal uart_data_read_nxt : std_logic;
begin
w3_uart_send(byte_t'range),
tx_rdy,
bd_rate,
- w1_st_co(0)
+ w1_st_co(16)
);
rs232_rx_inst : rs232_rx
if (reset = RESET_VALUE) then
w1_st_co <= (others=>'0');
w2_uart_config(31 downto 16) <= (others=>'0');
- -- todo mit einer konstante versehen
- w2_uart_config(15 downto 0) <= x"01B2";
+ w2_uart_config(15 downto 0) <= std_logic_vector(to_unsigned(CLK_PER_BAUD, 16));
w3_uart_send <= (others=>'0');
w4_uart_receive <= (others=>'0');
tx_rdy_int <= '0';
new_tx_data <= '0';
- uart_data_read <= '0';
uart_int <= '0';
elsif rising_edge(clk) then
w4_uart_receive <= w4_uart_receive_nxt;
new_tx_data <= new_tx_data_nxt;
tx_rdy_int <= tx_rdy;
- uart_data_read <= uart_data_read_nxt;
uart_int <= uart_int_nxt;
end if;
end process syn;
-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
-gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read)
+gwriten : process
+ (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read_nxt)
variable tmp_data : gp_register_t;
when "01" =>
w2_uart_config_nxt <= tmp_data;
when "10" =>
- w1_st_co_nxt(16) <= '1'; -- busy flag set
+ w1_st_co_nxt(0) <= '1'; -- busy flag set
w3_uart_send_nxt <= tmp_data;
when "11" =>
--w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
end if;
if tx_rdy = '1' and tx_rdy_int = '0' then
- w1_st_co_nxt(16) <= '0'; -- busy flag reset
+ w1_st_co_nxt(0) <= '0'; -- busy flag reset
end if;
if new_bus_rx = '1' then
w4_uart_receive_nxt(7 downto 0) <= rx_data;
- w1_st_co_nxt(17) <= '1';
+ w1_st_co_nxt(1) <= '1';
uart_int_nxt <= '1';
end if;
- if (uart_data_read = '1' and w1_st_co(17) = '1' and ext_reg.sel = '1') then
- w1_st_co_nxt(17) <= '0';
+ if (uart_data_read_nxt = '1' and w1_st_co(1) = '1' and ext_reg.sel = '1') then
+ w1_st_co_nxt(1) <= '0';
end if;
end process gwriten;