uart_tx: minimale anpassungen (wollt nur mal drueber schauen...)

[calu.git] / cpu / src / extension_uart_b.vhd

diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd
index 5dd8774d76565c34f97fa37b6a957f79164e261e..99278a970284bbf806e13c099c2b001745693660 100644 (file)
--- a/cpu/src/extension_uart_b.vhd
+++ b/cpu/src/extension_uart_b.vhd
@@ -15,6 +15,10 @@ signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send,
 signal new_bus_rx,new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
 signal         bd_rate : baud_rate_l;
 signal rx_data : std_logic_vector(7 downto 0);
+
+signal uart_int_nxt : std_logic;
+signal uart_data_read_nxt : std_logic;
+
 begin
 
 
@@ -35,12 +39,13 @@ port map(
        w3_uart_send(byte_t'range),
        tx_rdy,
        bd_rate,
-       w1_st_co(0)
+       w1_st_co(16)
 );
 
 rs232_rx_inst : rs232_rx
 generic        map(
-               RESET_VALUE
+               RESET_VALUE,
+               2
                )
 port map(
        --System inputs
@@ -52,7 +57,8 @@ port map(
 
        --From/to sendlogic
        new_bus_rx,
-       rx_data
+       rx_data,
+       bd_rate
 );
 
 
@@ -60,32 +66,36 @@ port map(
 
 syn : process (clk, reset)
 begin
-        if (reset = RESET_VALUE) then
-               w1_st_co <= (others=>'0');
-               w2_uart_config <= (others=>'0');
-               w3_uart_send <= (others=>'0');
-               w4_uart_receive <= (others=>'0');
-               tx_rdy_int <= '0';
-               new_tx_data <= '0';
-
-        elsif rising_edge(clk) then            
-               w1_st_co <= w1_st_co_nxt;
-               w2_uart_config <= w2_uart_config_nxt;
-               w3_uart_send <= w3_uart_send_nxt;
-               w4_uart_receive <= w4_uart_receive_nxt;
-               new_tx_data <= new_tx_data_nxt;
-               tx_rdy_int <= tx_rdy;
-        end if;
+   if (reset = RESET_VALUE) then
+                       w1_st_co <= (others=>'0');
+                       w2_uart_config(31 downto 16) <= (others=>'0');
+                       w2_uart_config(15 downto 0) <= std_logic_vector(to_unsigned(CLK_PER_BAUD, 16));
+                       w3_uart_send <= (others=>'0');
+                       w4_uart_receive <= (others=>'0');
+                       tx_rdy_int <= '0';
+                       new_tx_data <= '0';
+                       uart_int <= '0';
+
+       elsif rising_edge(clk) then            
+                       w1_st_co <= w1_st_co_nxt;
+                       w2_uart_config <= w2_uart_config_nxt;
+                       w3_uart_send <= w3_uart_send_nxt;
+                       w4_uart_receive <= w4_uart_receive_nxt;
+                       new_tx_data <= new_tx_data_nxt;
+                       tx_rdy_int <= tx_rdy;
+                       uart_int <= uart_int_nxt;
+   end if;
 end process syn;
 
 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
 
-gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int)
+gwriten : process
+       (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read_nxt)
 
 variable tmp_data  : gp_register_t;
 
 begin
-
+               uart_int_nxt <= '0';
                w1_st_co_nxt <= w1_st_co;
                w2_uart_config_nxt <= w2_uart_config;
                w3_uart_send_nxt <= w3_uart_send;
@@ -112,18 +122,28 @@ begin
                when "01" =>
                        w2_uart_config_nxt <= tmp_data;
                when "10" =>
-                       w1_st_co_nxt(16) <= '1'; -- busy flag set
+                       w1_st_co_nxt(0) <= '1'; -- busy flag set
                        w3_uart_send_nxt <= tmp_data;
                when "11" =>
-                       w4_uart_receive_nxt <= tmp_data;
+                       --w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
                when others => null;
                end case;
        end if;
 
        if  tx_rdy = '1' and tx_rdy_int = '0' then
-               w1_st_co_nxt(16) <= '0'; -- busy flag reset     
+               w1_st_co_nxt(0) <= '0'; -- busy flag reset      
        end if;
 
+       if new_bus_rx = '1' then
+               w4_uart_receive_nxt(7 downto 0) <= rx_data;
+               w1_st_co_nxt(1) <= '1';
+               uart_int_nxt <= '1';
+       end if;
+       
+       if (uart_data_read_nxt = '1' and w1_st_co(1) = '1' and ext_reg.sel = '1') then
+               w1_st_co_nxt(1) <= '0';
+       end if;
+       
 end process gwriten;
 
 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
@@ -131,6 +151,9 @@ gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receiv
 variable tmp_data  : gp_register_t;
 
 begin
+
+       uart_data_read_nxt <= '0';
+
        if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
                case ext_reg.addr(1 downto 0) is
                when "00" => 
@@ -179,7 +202,8 @@ begin
                        end if;
                        data_out <= tmp_data;
                when "11" =>
-                       tmp_data := (others =>'0');                     
+                       tmp_data := (others =>'0');     
+                       uart_data_read_nxt <= '1';
                        if ext_reg.byte_en(0) = '1' then
                                tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
                        end if;