copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / extension_uart.vhd

diff --git a/cpu/src/extension_uart.vhd b/cpu/src/extension_uart.vhd
index 9a31d1db983100fc132bd90fc526dce5ba2d4cb9..b8b7674a1ea4288ed40de3b6101c3db1b2f62b81 100644 (file)
--- a/cpu/src/extension_uart.vhd
+++ b/cpu/src/extension_uart.vhd
@@ -1,8 +1,30 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
+use work.extension_pkg.all;
 use work.extension_uart_pkg.all;
 
 
@@ -10,7 +32,8 @@ entity extension_uart is
 
        generic (
                        -- active reset value
-                       RESET_VALUE : std_logic
+                       RESET_VALUE : std_logic;
+                       CLK_PER_BAUD : integer
                        );
        port(
                --System inputs
@@ -19,8 +42,10 @@ entity extension_uart is
                -- general extension interface                  
                        ext_reg  : in extmod_rec;
                        data_out : out gp_register_t;
-               -- Input
 
+                       uart_int : out std_logic;
+               -- Input
+                       bus_rx : in std_logic;
                -- Ouput
                        bus_tx : out std_logic
                );