7seg small changes

[calu.git] / cpu / src / extension_7seg_b.vhd

diff --git a/cpu/src/extension_7seg_b.vhd b/cpu/src/extension_7seg_b.vhd
index 0e58cca78a7924b6c4cd4836f41b06742823407b..a78da17d9339f43a4a09ddacaa2714d60d606267 100755 (executable)
--- a/cpu/src/extension_7seg_b.vhd
+++ b/cpu/src/extension_7seg_b.vhd
@@ -45,27 +45,23 @@ end process;
 \r
 seg_asyn: process(s_state, ext_reg_r)  \r
 \r
-variable tmp_data  : byte_t;\r
-\r
 begin\r
        s_state_nxt <= s_state; \r
-       tmp_data := (others =>'0');                     \r
 \r
        if ext_reg_r.sel = '1' and ext_reg_r.wr_en = '1' then\r
 \r
-               tmp_data(byte_t'range) :=ext_reg_r.data(byte_t'range);\r
-\r
-               s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));\r
-               s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));\r
-               s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));\r
-               s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));\r
 \r
                case ext_reg_r.byte_en(1 downto 0) is\r
-               when "01" => s_state_nxt.digit3 <= digit_decode("11111");\r
                when "00" => null;\r
-               when "10" => null;\r
-               when "11" => null;\r
-               when others => null;\r
+                       s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));\r
+                       s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));\r
+                       s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));\r
+                       s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));\r
+               when others => \r
+                       s_state_nxt.digit0 <= (others => '1');\r
+                       s_state_nxt.digit1 <= (others => '1');\r
+                       s_state_nxt.digit2 <= (others => '1');\r
+                       s_state_nxt.digit3 <= (others => '1');\r
                end case;\r
 \r
 \r