copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / execute_stage.vhd

diff --git a/cpu/src/execute_stage.vhd b/cpu/src/execute_stage.vhd
index 9ca96bcf2e9921f9386e4e34c4993b05d3025937..414ba7c91da63f1a6c9804b065697e65fb9d5f6f 100644 (file)
--- a/cpu/src/execute_stage.vhd
+++ b/cpu/src/execute_stage.vhd
@@ -1,12 +1,38 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
+use work.common_pkg.all;
+use work.alu_pkg.all;
+use work.extension_pkg.all;
+--use work.gpm_pkg.all;
+
 entity execute_stage is
 
        generic (
                        -- active reset value
-                       RESET_VALUE : std_logic;
+                       RESET_VALUE : std_logic
                        -- active logic value
                        --LOGIC_ACT : std_logic;
                        
@@ -16,19 +42,24 @@ entity execute_stage is
                        clk : in std_logic;
                        reset : in std_logic;
                         dec_instr : in dec_op;
-
-                --System output
-                        result : out gp_register_t;--reg
-                        result_addr : out gp_addr_t;--reg
-                        addr : out word_t; --memaddr
-                        data : out gp_register_t; --mem data --ureg
-                        alu_jump : out std_logic;--reg
-                        brpr  : out std_logic;  --reg
-                        wr_en : out std_logic;--regop --reg
-                        dmem  : out std_logic;--memop
-                        dmem_wr_en : out std_logic;
-                        hword  : out std_logic;
-                        byte_s : out std_logic
+                       regfile_val : in gp_register_t;
+                       reg_we : in std_logic;
+                       reg_addr : in gp_addr_t;
+                       ext_reg  : in extmod_rec;
+            --System output
+            result : out gp_register_t;--reg
+            result_addr : out gp_addr_t;--reg
+            addr : out word_t; --memaddr
+            data : out gp_register_t; --mem data --ureg
+            alu_jump : out std_logic;--reg
+            brpr  : out std_logic;  --reg
+            wr_en : out std_logic;--regop --reg
+            dmem  : out std_logic;--memop
+            dmem_write_en : out std_logic;
+            hword  : out std_logic;
+            byte_s : out std_logic;
+                               
+                       ext_data_out : out gp_register_t
                );
                
 end execute_stage;