copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / exec_op / shift_op_b.vhd

diff --git a/cpu/src/exec_op/shift_op_b.vhd b/cpu/src/exec_op/shift_op_b.vhd
old mode 100755 (executable)
new mode 100644 (file)
index 0b5a73c..d009261
--- a/cpu/src/exec_op/shift_op_b.vhd
+++ b/cpu/src/exec_op/shift_op_b.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
@@ -7,34 +28,33 @@ use work.alu_pkg.all;
 
 architecture shift_op of exec_op is
 
-       signal logic, ls, carry : std_logic;
+       signal arith, rs, carry : std_logic;
 
 begin
 
-       logic <=  op_detail(LOG_OPT);
-       ls      <=  op_detail(LEFT_OPT);
+       arith <=  op_detail(ARITH_OPT);
+       rs      <=  op_detail(RIGHT_OPT);
        carry <= op_detail(CARRY_OPT);
 
-calc: process(left_operand, right_operand, logic,ls, carry, alu_state)
+calc: process(left_operand, right_operand, arith,rs, carry, alu_state)
                variable alu_result_v : alu_result_rec;
                variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);
                variable tmp_sb : std_logic;
-       begin
+begin
                alu_result_v := alu_state;
                
-               if ls = '1' then
-                       tmp_sb := (carry and alu_state.status.carry and logic);
-                       tmp_shift :=  to_bitvector(alu_state.status.carry & left_operand & tmp_sb);
-                       tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
-                       
-                       alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);
-                       
-               else
-                       tmp_sb := (carry and alu_state.status.carry and logic) or (not(logic) and left_operand(gp_register_t'high));
+                if rs = '1' then   
+                       tmp_sb := (carry and alu_state.status.carry and not(arith)) or (arith and left_operand(gp_register_t'high));
                        tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry);
-                       tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
+                       tmp_shift := tmp_shift sra to_integer(unsigned(right_operand(SHIFT_WIDTH-1 downto 0)));
                        
                        alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0);
+               else 
+                       tmp_sb := (carry and alu_state.status.carry and not(arith));
+                       tmp_shift :=  to_bitvector(alu_state.status.carry & left_operand & tmp_sb);
+                       tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand(SHIFT_WIDTH-1 downto 0)));
+                       
+                       alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);
                end if;
                
                alu_result_v.result := to_stdlogicvector(tmp_shift)(gp_register_t'length downto 1);