fib

[calu.git] / cpu / src / decoder_b.vhd

diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd
index 65375557c8967a5304a91902f1b9b976b8d93973..01c11f07b82393499d2f094f7677825b52158672 100644 (file)
--- a/cpu/src/decoder_b.vhd
+++ b/cpu/src/decoder_b.vhd
@@ -215,19 +215,28 @@ begin
 --     when "01110" =>         --ldw
                instr_s.reg_dest_addr := instruction(22 downto 19);
                instr_s.reg_src1_addr := instruction(18 downto 15);
-               instr_s.immediate(15 downto 0) := instruction(18 downto 3);
                instr_s.signext := instruction(2);
                instr_s.high_low := instruction(1);
 
                instr_s.op_group := LDST_OP;
                instr_s.op_detail(NO_PSW_OPT) := '1';
 
-               if (instr_s.opcode = "11010") then
+               if (instr_s.opcode = "11010") then              --ldi
+                       if (instr_s.high_low = '1') then
+                               instr_s.immediate(31 downto 16) := instruction(18 downto 3);
+                               instr_s.immediate(15 downto 0) := (others => '0');
+                       else
+                               instr_s.immediate(15 downto 0) := instruction(18 downto 3);
+                               instr_s.immediate(31 downto 16) := (others => '0');
+
+                               --instr_s.immediate(11 downto 0) := instruction(14 downto 3);
+                               --instr_s.immediate(WORD_WIDTH-1 downto 12) := (others => '0');
+                       end if;                 
+
                        if (instr_s.signext = '1' and instr_s.immediate(11) = '1') then
                                instr_s.immediate(31 downto 16) := (others => '1');
                        end if;
-                       instr_s.immediate(11 downto 0) := instruction(14 downto 3);
-                       instr_s.immediate(WORD_WIDTH-1 downto 12) := (others => '0');
+
                        instr_s.op_detail(IMM_OPT) := '1';
                end if;
        end if;