-- end record;
-- output logic incl. bypassing reg-file
-output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data)
+output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data, nop)
begin
to_next_stage.src1 <= reg1_rd_data;
to_next_stage.src2 <= reg2_rd_data;
+ if (nop = '1') then
+ to_next_stage.condition <= "1111";
+ end if;
+
end process;
branch_prediction_bit <= '0';
if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
- branch_prediction_res <= instr_spl.immediate; --both 32 bit
+ branch_prediction_res <= std_logic_vector(unsigned(instr_spl.immediate) + unsigned(prog_cnt)); --both 32 bit
branch_prediction_bit <= '1';
end if;