+-- `Deep Thought', a softcore CPU implemented on a FPGA
+--
+-- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+-- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+-- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+-- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+-- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+
library IEEE;
use IEEE.std_logic_1164.all;
-- fills output register
-to_next: process(instr_spl)
+to_next: process(instr_spl, prog_cnt)
begin
dec_op_inst_nxt.condition <= instr_spl.predicates;
rtw_rec_nxt.reg1_addr <= instr_spl.reg_src1_addr;
rtw_rec_nxt.reg2_addr <= instr_spl.reg_src2_addr;
- if (instr_spl.op_detail(IMM_OPT) = '1') then
+ if (instr_spl.op_detail(IMM_OPT) = '1') then -- or instr_spl.op_group = LDST_OP
rtw_rec_nxt.immediate <= instr_spl.immediate;
rtw_rec_nxt.imm_set <= '1';
end if;
-- async process: calculates branch prediction
-br_pred: process(instr_spl)
+br_pred: process(instr_spl, prog_cnt, reset)
begin
branch_prediction_bit <= '0';
if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
- branch_prediction_res <= std_logic_vector(unsigned(instr_spl.immediate) + unsigned(prog_cnt)); --both 32 bit
+ if instr_spl.int = '0' then
+ branch_prediction_res <= std_logic_vector(unsigned(instr_spl.immediate) + unsigned(prog_cnt)); --both 32 bit
+ else
+ branch_prediction_res <= instr_spl.immediate;
+ end if;
branch_prediction_bit <= '1';
end if;
+ if reset = RESET_VALUE then
+ branch_prediction_bit <= '0';
+ end if;
+
end process;
end behav;