copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / decode_stage_b.vhd

diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd
index 14846b227dc9cf202181500064fa0dc3c5049968..4f6990148e2ba524e847b8435b519cfd8c50f9d7 100644 (file)
--- a/cpu/src/decode_stage_b.vhd
+++ b/cpu/src/decode_stage_b.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 
 use IEEE.std_logic_1164.all;
@@ -66,7 +87,8 @@ begin
                dec_op_inst.saddr1 <= (others => '0');
                dec_op_inst.saddr2 <= (others => '0');
                dec_op_inst.daddr <= (others => '0');
-
+               dec_op_inst.displacement <= (others => '0');
+               dec_op_inst.prog_cnt <= (others => '0');
 
        elsif rising_edge(clk) then
                rtw_rec <= rtw_rec_nxt;
@@ -92,7 +114,7 @@ end process;
 --     end record;
 
 -- output logic incl. bypassing reg-file
-output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data)
+output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data, nop)
 
 begin
 
@@ -100,11 +122,15 @@ begin
        to_next_stage.src1 <= reg1_rd_data;
        to_next_stage.src2 <= reg2_rd_data;
 
+       if (nop = '1') then
+               to_next_stage.condition <= "1111";
+       end if;
+
 end process;
 
 
 -- fills output register
-to_next: process(instr_spl)
+to_next: process(instr_spl, prog_cnt)
 
 begin
        dec_op_inst_nxt.condition <= instr_spl.predicates;
@@ -116,6 +142,8 @@ begin
        dec_op_inst_nxt.saddr2 <= instr_spl.reg_src2_addr;
        dec_op_inst_nxt.daddr <= instr_spl.reg_dest_addr; --(others => '0');
        dec_op_inst_nxt.op_group <= instr_spl.op_group;
+       dec_op_inst_nxt.displacement <= instr_spl.displacement;
+       dec_op_inst_nxt.prog_cnt <= prog_cnt;
 
 end process;
 
@@ -152,10 +180,11 @@ begin
        rtw_rec_nxt.rtw_reg2 <= '0';
        rtw_rec_nxt.immediate <= (others => '0');
        rtw_rec_nxt.imm_set <= '0';
+--- ???? wieso
        rtw_rec_nxt.reg1_addr <= instr_spl.reg_src1_addr;
        rtw_rec_nxt.reg2_addr <= instr_spl.reg_src2_addr;
 
-       if (instr_spl.op_detail(IMM_OPT) = '1') then
+       if (instr_spl.op_detail(IMM_OPT) = '1') then -- or instr_spl.op_group = LDST_OP
                rtw_rec_nxt.immediate <= instr_spl.immediate;
                rtw_rec_nxt.imm_set <= '1';
        end if;
@@ -172,7 +201,7 @@ end process;
 
 
 -- async process: calculates branch prediction
-br_pred: process(instr_spl)
+br_pred: process(instr_spl, prog_cnt, reset)
 
 begin
 
@@ -180,10 +209,18 @@ begin
        branch_prediction_bit <= '0';
 
        if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
-               branch_prediction_res <= instr_spl.immediate;   --both 32 bit
+               if instr_spl.int = '0' then             
+                       branch_prediction_res <= std_logic_vector(unsigned(instr_spl.immediate) + unsigned(prog_cnt));  --both 32 bit
+               else 
+                       branch_prediction_res <= instr_spl.immediate;
+               end if;
                branch_prediction_bit <= '1';
        end if;
 
+       if reset = RESET_VALUE then
+               branch_prediction_bit <= '0';
+       end if;
+
 end process;
 
 end behav;