copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / decode_stage.vhd

diff --git a/cpu/src/decode_stage.vhd b/cpu/src/decode_stage.vhd
index 4be1c3ec0dbde87c1b7ae9b380ea496891df82f2..8fb9df140207c138813870bbcbd0efe6d56a6ce8 100644 (file)
--- a/cpu/src/decode_stage.vhd
+++ b/cpu/src/decode_stage.vhd
@@ -1,20 +1,64 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
+use work.core_pkg.all;
+use work.common_pkg.all;
+
+
 entity decode_stage is
 
        generic (
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic;
+                       LOGIC_ACT : std_logic
                        
                        );
        port(
                --System inputs
                        clk : in std_logic;
                        reset : in std_logic;
+
+               --Data inputs
+                       instruction : in instruction_word_t;
+                       prog_cnt : in instruction_addr_t;
+                       reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+                       reg_wr_data : in gp_register_t;
+                       reg_we : in std_logic;
+                       nop : in std_logic;
+
+               --Data outputs
+--                     reg1_rd_data : out gp_register_t;
+--                     reg2_rd_data : out gp_register_t;
+                       branch_prediction_res : out instruction_addr_t;
+                       branch_prediction_bit : out std_logic;
+
+                       to_next_stage : out dec_op
+                       
                );
                
 end decode_stage;
+
+