ram: reducing instr- and dataram

[calu.git] / cpu / src / decode_stage.vhd

diff --git a/cpu/src/decode_stage.vhd b/cpu/src/decode_stage.vhd
index 2b0cf49a62513e8c4060c39d4afca6ba2011977f..620a2ccdbf048113e0b4c9b04187b052e19ba816 100644 (file)
--- a/cpu/src/decode_stage.vhd
+++ b/cpu/src/decode_stage.vhd
@@ -22,15 +22,19 @@ entity decode_stage is
 
                --Data inputs
                        instruction : in instruction_word_t;
+                       prog_cnt : in instruction_addr_t;
                        reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                        reg_wr_data : in gp_register_t;
                        reg_we : in std_logic;
+                       nop : in std_logic;
 
                --Data outputs
-                       reg1_rd_data : out gp_register_t;
-                       reg2_rd_data : out gp_register_t;
-                       branch_prediction_res : out instruction_word_t;
-                       branch_prediction_bit : out std_logic
+--                     reg1_rd_data : out gp_register_t;
+--                     reg2_rd_data : out gp_register_t;
+                       branch_prediction_res : out instruction_addr_t;
+                       branch_prediction_bit : out std_logic;
+
+                       to_next_stage : out dec_op
                        
                );