-- uart
bus_tx : out std_logic;
bus_rx : in std_logic;
+ led1 : out std_logic;
sseg0 : out std_logic_vector(0 to 6);
sseg1 : out std_logic_vector(0 to 6);
begin
- if sys_res = '0' then
+ if sys_res = '1' then
+ led1 <= '0';
-- vers.result <= (others => '0');
-- vers.result_addr <= (others => '0');
-- vers.address <= (others => '0');
sync <= (others => '0');
elsif rising_edge(sys_clk) then
+ led1 <= '1';
-- vers <= vers_nxt;
- sync(1) <= sys_res;
+ sync(1) <= not sys_res;
for i in 2 to SYNC_STAGES loop
sync(i) <= sync(i - 1);
end loop;