copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index f3e132328db24cfdc16516be3954a6a24673f47a..f7e0a75c1a4c9988e29ecb8b9efbee829502fa29 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -1,3 +1,24 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
@@ -12,18 +33,18 @@ entity core_top is
                --System input pins
                   sys_res : in std_logic;
                        soft_res : in std_logic;
-                       sys_clk : in std_logic;
+                       sys_clk_in : in std_logic;
 --                     result : out gp_register_t;
 --                     reg_wr_data : out gp_register_t
                  -- uart
                        bus_tx : out std_logic;
                        bus_rx : in std_logic;
-                       led2 : out std_logic;
+                       led2 : out std_logic
                        
-                       sseg0 : out std_logic_vector(0 to 6);
-                       sseg1 : out std_logic_vector(0 to 6);
-                       sseg2 : out std_logic_vector(0 to 6);
-                       sseg3 : out std_logic_vector(0 to 6)
+                       --sseg0 : out std_logic_vector(0 to 6);
+                       --sseg1 : out std_logic_vector(0 to 6);
+                       --sseg2 : out std_logic_vector(0 to 6);
+                       --sseg3 : out std_logic_vector(0 to 6)
                );
 
 end core_top;
@@ -33,6 +54,8 @@ architecture behav of core_top is
                constant SYNC_STAGES : integer := 2;
                constant RESET_VALUE : std_logic := '0';
 
+               signal sys_clk : std_logic;
+
                signal jump_result : instruction_addr_t;
                signal jump_result_pin : instruction_addr_t;
                signal prediction_result_pin : instruction_addr_t;
@@ -74,8 +97,23 @@ architecture behav of core_top is
                 signal im_addr, im_data : gp_register_t;
                 
                 signal vers, vers_nxt : exec2wb_rec;
+
+
+       component pll
+               PORT
+               (
+                       inclk0 : IN STD_LOGIC  := '0';
+                       c0          : OUT STD_LOGIC
+               );
+       end component;
 begin
 
+       pll_inst : pll PORT MAP (
+               inclk0 => sys_clk_in,
+               c0     => sys_clk
+       );
+
+
        fetch_st : fetch_stage
                generic map (
        
@@ -157,13 +195,14 @@ begin
 --
 
                        writeback_st : writeback_stage
-                generic map('0', '1', "altera", 2083)
+                generic map('0', '1', "altera", 5208)
                 port map(sys_clk, sys_res_n and soft_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
                                -- instruction memory program port :D
                                new_im_data, im_addr, im_data,
-                               sseg0, sseg1, sseg2, sseg3, int_req);
+                               --sseg0, sseg1, sseg2, sseg3,
+                                int_req);
 
 
 syn: process(sys_clk, sys_res, soft_res)